Merge tag 'kvm-arm-for-3.17' of...

  the kernel image will be entered must be initialised by software at a

  higher exception level to prevent execution in an UNKNOWN state.

  For systems with a GICv3 interrupt controller:

  - If EL3 is present:

    ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.

    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.

  - If the kernel is entered at EL1:

    ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1

    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.

The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.

* ARM Generic Interrupt Controller, version 3

AArch64 SMP cores are often associated with a GICv3, providing Private

Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),

Software Generated Interrupts (SGI), and Locality-specific Peripheral

Interrupts (LPI).

Main node required properties:

- compatible : should at least contain  "arm,gic-v3".

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. Must be a single cell with a value of at least 3.

  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI

  interrupts. Other values are reserved for future use.

  The 2nd cell contains the interrupt number for the interrupt type.

  SPI interrupts are in the range [0-987]. PPI interrupts are in the

  range [0-15].

  The 3rd cell is the flags, encoded as follows:

	bits[3:0] trigger type and level flags.

		1 = edge triggered

		4 = level triggered

  Cells 4 and beyond are reserved for future use. When the 1st cell

  has a value of 0 or 1, cells 4 and beyond act as padding, and may be

  ignored. It is recommended that padding cells have a value of 0.

- reg : Specifies base physical address(s) and size of the GIC

  registers, in the following order:

  - GIC Distributor interface (GICD)

  - GIC Redistributors (GICR), one range per redistributor region

  - GIC CPU interface (GICC)

  - GIC Hypervisor interface (GICH)

  - GIC Virtual CPU interface (GICV)

  GICC, GICH and GICV are optional.

- interrupts : Interrupt source of the VGIC maintenance interrupt.

Optional

- redistributor-stride : If using padding pages, specifies the stride

  of consecutive redistributors. Must be a multiple of 64kB.

- #redistributor-regions: The number of independent contiguous regions

  occupied by the redistributors. Required if more than one such

  region is present.

Examples:

	gic: interrupt-controller@2cf00000 {

		compatible = "arm,gic-v3";

		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x0 0x2f000000 0 0x10000>,	// GICD

		      <0x0 0x2f100000 0 0x200000>,	// GICR

		      <0x0 0x2c000000 0 0x2000>,	// GICC

		      <0x0 0x2c010000 0 0x2000>,	// GICH

		      <0x0 0x2c020000 0 0x2000>;	// GICV

		interrupts = <1 9 4>;

	};

	gic: interrupt-controller@2c010000 {

		compatible = "arm,gic-v3";

		#interrupt-cells = <3>;

		interrupt-controller;

		redistributor-stride = <0x0 0x40000>;	// 256kB stride

		#redistributor-regions = <2>;

		reg = <0x0 0x2c010000 0 0x10000>,	// GICD

		      <0x0 0x2d000000 0 0x800000>,	// GICR 1: CPUs 0-31

		      <0x0 0x2e000000 0 0x800000>;	// GICR 2: CPUs 32-63

		      <0x0 0x2c040000 0 0x2000>,	// GICC

		      <0x0 0x2c060000 0 0x2000>,	// GICH

		      <0x0 0x2c080000 0 0x2000>;	// GICV

		interrupts = <1 9 4>;

	};

#define ARM_EXCEPTION_FIQ	  6

#define ARM_EXCEPTION_HVC	  7

/*

 * The rr_lo_hi macro swaps a pair of registers depending on

 * current endianness. It is used in conjunction with ldrd and strd

 * instructions that load/store a 64-bit value from/to memory to/from

 * a pair of registers which are used with the mrrc and mcrr instructions.

 * If used with the ldrd/strd instructions, the a1 parameter is the first

 * source/destination register and the a2 parameter is the second

 * source/destination register. Note that the ldrd/strd instructions

 * already swap the bytes within the words correctly according to the

 * endianness setting, but the order of the registers need to be effectively

 * swapped when used with the mrrc/mcrr instructions.

 */

#ifdef CONFIG_CPU_ENDIAN_BE8

#define rr_lo_hi(a1, a2) a2, a1

#else

#define rr_lo_hi(a1, a2) a1, a2

#endif

#ifndef __ASSEMBLY__

struct kvm;

struct kvm_vcpu;

		default:

			return be32_to_cpu(data);

		}

	} else {

		switch (len) {

		case 1:

			return data & 0xff;

		case 2:

			return le16_to_cpu(data & 0xffff);

		default:

			return le32_to_cpu(data);

		}

	}

	return data;		/* Leave LE untouched */

}

static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,

		default:

			return cpu_to_be32(data);

		}

	} else {

		switch (len) {

		case 1:

			return data & 0xff;

		case 2:

			return cpu_to_le16(data & 0xffff);

		default:

			return cpu_to_le32(data);

		}

	}

	return data;		/* Leave LE untouched */

}

#endif /* __ARM_KVM_EMULATE_H__ */

	return 0;

}

static inline void vgic_arch_setup(const struct vgic_params *vgic)

{

	BUG_ON(vgic->type != VGIC_V2);

}

int kvm_perf_init(void);

int kvm_perf_teardown(void);

u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, u64 regid);

int kvm_arm_timer_set_reg(struct kvm_vcpu *, u64 regid, u64 value);

#endif /* __ARM_KVM_HOST_H__ */