Commit 5d571068 authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Lucas De Marchi
Browse files

drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers 



Tiger Lake has a new register offset for DC5 and DC6 residency counters.

v2:
  - Rename registers since they are not in the CSR memory range
    (requested by Anshuman)
  - Fix type (requested by Matthew)

Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190726002412.5827-2-lucas.demarchi@intel.com
parent 01158da7

drivers/gpu/drm/i915/i915_debugfs.c

+13 −8
Original line number Diff line number Diff line
@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) 
	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	struct intel_csr *csr;

	i915_reg_t dc5_reg, dc6_reg = {};



	if (!HAS_CSR(dev_priv))

		return -ENODEV;
@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused) 
	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),

		   CSR_VERSION_MINOR(csr->version));



	if (WARN_ON(INTEL_GEN(dev_priv) > 11))

		goto out;



	seq_printf(m, "DC3 -> DC5 count: %d\n",

		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :

						    SKL_CSR_DC3_DC5_COUNT));

	if (INTEL_GEN(dev_priv) >= 12) {

		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;

		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;

	} else {

		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :

						 SKL_CSR_DC3_DC5_COUNT;

		if (!IS_GEN9_LP(dev_priv))

		seq_printf(m, "DC5 -> DC6 count: %d\n",

			   I915_READ(SKL_CSR_DC5_DC6_COUNT));

			dc6_reg = SKL_CSR_DC5_DC6_COUNT;

	}



	seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));

	if (dc6_reg.reg)

		seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));



out:

	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -7271,6 +7271,8 @@ enum { 
#define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)

#define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)

#define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)

#define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)

#define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)



/* interrupts */

#define DE_MASTER_IRQ_CONTROL   (1 << 31)

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