Commit 5d43a1de authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx 

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
  dmaengine: at_hdmac: fix buffer transfer size specification
  fsldma: fix issue of slow dma
  dmaengine i.MX SDMA: initialize on module_init
  dma : EG20T PCH: Fix miss-setting DMA descriptor
  intel_mid_dma: fix section mismatch warnings
  dmaengine: imx-sdma: fix bug in buffer descriptor initialization
  drivers/dma/ppc4xx: Use printf extension %pR for struct resource
  drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGS
  drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGS
  dma: intel_mid_dma: fix double free on mid_setup_dma error path
  dma: imx-dma: fix imxdma_probe error path
parents 7103b71b 59a609d9

drivers/dma/Makefile

+2 −2
Original line number Diff line number Diff line 
ifeq ($(CONFIG_DMADEVICES_DEBUG),y)

	EXTRA_CFLAGS	+= -DDEBUG

	ccflags-y	+= -DDEBUG

endif

ifeq ($(CONFIG_DMADEVICES_VDEBUG),y)

	EXTRA_CFLAGS	+= -DVERBOSE_DEBUG

	ccflags-y	+= -DVERBOSE_DEBUG

endif



obj-$(CONFIG_DMA_ENGINE) += dmaengine.o

drivers/dma/at_hdmac.c

+1 −1
Original line number Diff line number Diff line
@@ -722,7 +722,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 
			desc->lli.daddr = mem;

			desc->lli.ctrla = ctrla

					| ATC_DST_WIDTH(mem_width)

					| len >> mem_width;

					| len >> reg_width;

			desc->lli.ctrlb = ctrlb;



			if (!first) {

drivers/dma/fsldma.c

+4 −2
Original line number Diff line number Diff line
@@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan) 
		 * EIE - Error interrupt enable

		 * EOSIE - End of segments interrupt enable (basic mode)

		 * EOLNIE - End of links interrupt enable

		 * BWC - Bandwidth sharing among channels

		 */

		DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE

				| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);

		DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC

				| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE

				| FSL_DMA_MR_EOSIE, 32);

		break;

	case FSL_DMA_IP_83XX:

		/* Set the channel to below modes:

drivers/dma/fsldma.h

+8 −1
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.

 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.

 *

 * Author:

 *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -36,6 +36,13 @@ 
#define FSL_DMA_MR_DAHE		0x00002000

#define FSL_DMA_MR_SAHE		0x00001000



/*

 * Bandwidth/pause control determines how many bytes a given

 * channel is allowed to transfer before the DMA engine pauses

 * the current channel and switches to the next channel

 */

#define FSL_DMA_MR_BWC         0x08000000



/* Special MR definition for MPC8349 */

#define FSL_DMA_MR_EOTIE	0x00000080

#define FSL_DMA_MR_PRC_RM	0x00000800

drivers/dma/imx-dma.c

+1 −1
Original line number Diff line number Diff line
@@ -379,7 +379,7 @@ static int __init imxdma_probe(struct platform_device *pdev) 
	return 0;



err_init:

	while (i-- >= 0) {

	while (--i >= 0) {

		struct imxdma_channel *imxdmac = &imxdma->channel[i];

		imx_dma_free(imxdmac->imxdma_channel);

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE