Commit 5cea24c5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm 

Pull second set of ARM updates from Russell King:
 "This is the second set of ARM updates for this merge window.

  Contained within are changes to allow the kernel to boot in hypervisor
  mode on CPUs supporting virtualization, and cache flushing support to
  the point of inner sharable unification, which are used by the
  suspend/resume code to avoid having to do a full cache flush.

  Also included is one fix for VFP code identified by Michael Olbrich."

* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: vfp: fix saving d16-d31 vfp registers on v6+ kernels
  ARM: 7549/1: HYP: fix boot on some ARM1136 cores
  ARM: 7542/1: mm: fix cache LoUIS API for xscale and feroceon
  ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API
  ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
  ARM: kernel: update cpu_suspend code to use cache LoUIS operations
  ARM: mm: rename jump labels in v7_flush_dcache_all function
  ARM: mm: implement LoUIS API for cache maintenance ops
  ARM: virt: arch_timers: enable access to physical timers
  ARM: virt: Add CONFIG_ARM_VIRT_EXT option
  ARM: virt: Add boot-time diagnostics
  ARM: virt: Update documentation for hyp mode entry support
  ARM: zImage/virt: hyp mode entry support for the zImage loader
  ARM: virt: allow the kernel to be entered in HYP mode
  ARM: opcodes: add __ERET/__MSR_ELR_HYP instruction encoding
parents 2fc07efa a0f0dd57

Documentation/arm/Booting

+21 −1
Original line number Diff line number Diff line
@@ -154,13 +154,33 @@ In either case, the following conditions must be met: 


- CPU mode

  All forms of interrupts must be disabled (IRQs and FIQs)

  The CPU must be in SVC mode.  (A special exception exists for Angel)



  For CPUs which do not include the ARM virtualization extensions, the

  CPU must be in SVC mode.  (A special exception exists for Angel)



  CPUs which include support for the virtualization extensions can be

  entered in HYP mode in order to enable the kernel to make full use of

  these extensions.  This is the recommended boot method for such CPUs,

  unless the virtualisations are already in use by a pre-installed

  hypervisor.



  If the kernel is not entered in HYP mode for any reason, it must be

  entered in SVC mode.



- Caches, MMUs

  The MMU must be off.

  Instruction cache may be on or off.

  Data cache must be off.



  If the kernel is entered in HYP mode, the above requirements apply to

  the HYP mode configuration in addition to the ordinary PL1 (privileged

  kernel modes) configuration.  In addition, all traps into the

  hypervisor must be disabled, and PL1 access must be granted for all

  peripherals and CPU resources for which this is architecturally

  possible.  Except for entering in HYP mode, the system configuration

  should be such that a kernel which does not include support for the

  virtualization extensions can boot correctly without extra help.



- The boot loader is expected to call the kernel image by jumping

  directly to the first instruction of the kernel image.

arch/arm/boot/compressed/.gitignore

+1 −0
Original line number Diff line number Diff line 
ashldi3.S

font.c

lib1funcs.S

hyp-stub.S

piggy.gzip

piggy.lzo

piggy.lzma

arch/arm/boot/compressed/Makefile

+8 −1
Original line number Diff line number Diff line
@@ -30,6 +30,10 @@ FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c 
OBJS		+= string.o

CFLAGS_string.o	:= -Os



ifeq ($(CONFIG_ARM_VIRT_EXT),y)

OBJS		+= hyp-stub.o

endif



#

# Architecture dependencies

#
@@ -126,7 +130,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) 
endif



ccflags-y := -fpic -fno-builtin -I$(obj)

asflags-y := -Wa,-march=all

asflags-y := -Wa,-march=all -DZIMAGE



# Supply kernel BSS size to the decompressor via a linker symbol.

KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
@@ -198,3 +202,6 @@ $(obj)/font.c: $(FONTC) 


$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)

	@sed "$(SEDFLAGS)" < $< > $@



$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S

	$(call cmd,shipped)

arch/arm/boot/compressed/head.S

+64 −7
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 * published by the Free Software Foundation.

 */

#include <linux/linkage.h>

#include <asm/assembler.h>



/*

 * Debugging stuff
@@ -132,7 +133,12 @@ start: 
		.word	start			@ absolute load/run zImage address

		.word	_edata			@ zImage end address

 THUMB(		.thumb			)

1:		mov	r7, r1			@ save architecture ID

1:

		mrs	r9, cpsr

#ifdef CONFIG_ARM_VIRT_EXT

		bl	__hyp_stub_install	@ get into SVC mode, reversibly

#endif

		mov	r7, r1			@ save architecture ID

		mov	r8, r2			@ save atags pointer



#ifndef __ARM_ARCH_2__
@@ -148,9 +154,9 @@ start: 
 ARM(		swi	0x123456	)	@ angel_SWI_ARM

 THUMB(		svc	0xab		)	@ angel_SWI_THUMB

not_angel:

		mrs	r2, cpsr		@ turn off interrupts to

		orr	r2, r2, #0xc0		@ prevent angel from running

		msr	cpsr_c, r2

		safe_svcmode_maskall r0

		msr	spsr_cxsf, r9		@ Save the CPU boot mode in

						@ SPSR

#else

		teqp	pc, #0x0c000003		@ turn off interrupts

#endif
@@ -350,6 +356,20 @@ dtb_check_done: 
		adr	r5, restart

		bic	r5, r5, #31



/* Relocate the hyp vector base if necessary */

#ifdef CONFIG_ARM_VIRT_EXT

		mrs	r0, spsr

		and	r0, r0, #MODE_MASK

		cmp	r0, #HYP_MODE

		bne	1f



		bl	__hyp_get_vectors

		sub	r0, r0, r5

		add	r0, r0, r10

		bl	__hyp_set_vectors

1:

#endif



		sub	r9, r6, r5		@ size to copy

		add	r9, r9, #31		@ rounded up to a multiple

		bic	r9, r9, #31		@ ... of 32 bytes
@@ -458,11 +478,29 @@ not_relocated: mov r0, #0 
		bl	decompress_kernel

		bl	cache_clean_flush

		bl	cache_off

		mov	r0, #0			@ must be zero

		mov	r1, r7			@ restore architecture number

		mov	r2, r8			@ restore atags pointer

 ARM(		mov	pc, r4	)		@ call kernel

 THUMB(		bx	r4	)		@ entry point is always ARM



#ifdef CONFIG_ARM_VIRT_EXT

		mrs	r0, spsr		@ Get saved CPU boot mode

		and	r0, r0, #MODE_MASK

		cmp	r0, #HYP_MODE		@ if not booted in HYP mode...

		bne	__enter_kernel		@ boot kernel directly



		adr	r12, .L__hyp_reentry_vectors_offset

		ldr	r0, [r12]

		add	r0, r0, r12



		bl	__hyp_set_vectors

		__HVC(0)			@ otherwise bounce to hyp mode



		b	.			@ should never be reached



		.align	2

.L__hyp_reentry_vectors_offset:	.long	__hyp_reentry_vectors - .

#else

		b	__enter_kernel

#endif



		.align	2

		.type	LC0, #object
@@ -1196,6 +1234,25 @@ memdump: mov r12, r0 
#endif



		.ltorg



#ifdef CONFIG_ARM_VIRT_EXT

.align 5

__hyp_reentry_vectors:

		W(b)	.			@ reset

		W(b)	.			@ undef

		W(b)	.			@ svc

		W(b)	.			@ pabort

		W(b)	.			@ dabort

		W(b)	__enter_kernel		@ hyp

		W(b)	.			@ irq

		W(b)	.			@ fiq

#endif /* CONFIG_ARM_VIRT_EXT */



__enter_kernel:

		mov	r0, #0			@ must be 0

 ARM(		mov	pc, r4	)		@ call kernel

 THUMB(		bx	r4	)		@ entry point is always ARM



reloc_code_end:



		.align

arch/arm/include/asm/assembler.h

+29 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 


#include <asm/ptrace.h>

#include <asm/domain.h>

#include <asm/opcodes-virt.h>



#define IOMEM(x)	(x)
@@ -239,6 +240,34 @@ 
	.endm

#endif



/*

 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is

 * a scratch register for the macro to overwrite.

 *

 * This macro is intended for forcing the CPU into SVC mode at boot time.

 * you cannot return to the original mode.

 *

 * Beware, it also clobers LR.

 */

.macro safe_svcmode_maskall reg:req

	mrs	\reg , cpsr

	mov	lr , \reg

	and	lr , lr , #MODE_MASK

	cmp	lr , #HYP_MODE

	orr	\reg , \reg , #PSR_I_BIT | PSR_F_BIT

	bic	\reg , \reg , #MODE_MASK

	orr	\reg , \reg , #SVC_MODE

THUMB(	orr	\reg , \reg , #PSR_T_BIT	)

	bne	1f

	orr	\reg, \reg, #PSR_A_BIT

	adr	lr, BSYM(2f)

	msr	spsr_cxsf, \reg

	__MSR_ELR_HYP(14)

	__ERET

1:	msr	cpsr_c, \reg

2:

.endm



/*

 * STRT/LDRT access macros with ARM and Thumb-2 variants

 */

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