Commit 5cb77114 authored by xinhui pan's avatar xinhui pan Committed by Alex Deucher
Browse files

drm/amdgpu: add ioctl query for enabled ras features (v2) 



Add a query for userspace to check which RAS features
are enabled.

v2: squash in warning fix

Signed-off-by: default avatarxinhui pan <xinhui.pan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ae363a21

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+10 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include "amdgpu_amdkfd.h"

#include "amdgpu_gem.h"

#include "amdgpu_display.h"

#include "amdgpu_ras.h"



static void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)

{
@@ -919,6 +920,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
	case AMDGPU_INFO_VRAM_LOST_COUNTER:

		ui32 = atomic_read(&adev->vram_lost_counter);

		return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;

	case AMDGPU_INFO_RAS_ENABLED_FEATURES: {

		struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);



		if (!ras)

			return -EINVAL;

		return copy_to_user(out, &ras->features,

				min_t(u32, size, sizeof(ras->features))) ?

			-EFAULT : 0;

	}

	default:

		DRM_DEBUG_KMS("Invalid request %d\n", info->query);

		return -EINVAL;

include/uapi/drm/amdgpu_drm.h

+31 −0
Original line number Diff line number Diff line
@@ -737,6 +737,37 @@ struct drm_amdgpu_cs_chunk_data { 
/* Number of VRAM page faults on CPU access. */

#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E

#define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F

/* query ras mask of enabled features*/

#define AMDGPU_INFO_RAS_ENABLED_FEATURES	0x20



/* RAS MASK: UMC (VRAM) */

#define AMDGPU_INFO_RAS_ENABLED_UMC			(1 << 0)

/* RAS MASK: SDMA */

#define AMDGPU_INFO_RAS_ENABLED_SDMA			(1 << 1)

/* RAS MASK: GFX */

#define AMDGPU_INFO_RAS_ENABLED_GFX			(1 << 2)

/* RAS MASK: MMHUB */

#define AMDGPU_INFO_RAS_ENABLED_MMHUB			(1 << 3)

/* RAS MASK: ATHUB */

#define AMDGPU_INFO_RAS_ENABLED_ATHUB			(1 << 4)

/* RAS MASK: PCIE */

#define AMDGPU_INFO_RAS_ENABLED_PCIE			(1 << 5)

/* RAS MASK: HDP */

#define AMDGPU_INFO_RAS_ENABLED_HDP			(1 << 6)

/* RAS MASK: XGMI */

#define AMDGPU_INFO_RAS_ENABLED_XGMI			(1 << 7)

/* RAS MASK: DF */

#define AMDGPU_INFO_RAS_ENABLED_DF			(1 << 8)

/* RAS MASK: SMN */

#define AMDGPU_INFO_RAS_ENABLED_SMN			(1 << 9)

/* RAS MASK: SEM */

#define AMDGPU_INFO_RAS_ENABLED_SEM			(1 << 10)

/* RAS MASK: MP0 */

#define AMDGPU_INFO_RAS_ENABLED_MP0			(1 << 11)

/* RAS MASK: MP1 */

#define AMDGPU_INFO_RAS_ENABLED_MP1			(1 << 12)

/* RAS MASK: FUSE */

#define AMDGPU_INFO_RAS_ENABLED_FUSE			(1 << 13)



#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0

#define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff

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