Merge tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

* Microchip PIC32 GPIO devices (PIO).

Required properties:

 - compatible: "microchip,pic32mzda-gpio"

 - reg: Base address and length for the device.

 - interrupts: The port interrupt shared by all pins.

 - gpio-controller: Marks the port as GPIO controller.

 - #gpio-cells: Two. The first cell is the pin number and

   the second cell is used to specify the gpio polarity as defined in

   defined in <dt-bindings/gpio/gpio.h>:

      0 = GPIO_ACTIVE_HIGH

      1 = GPIO_ACTIVE_LOW

      2 = GPIO_OPEN_DRAIN

 - interrupt-controller: Marks the device node as an interrupt controller.

 - #interrupt-cells: Two. The first cell is the GPIO number and second cell

   is used to specify the trigger type as defined in

   <dt-bindings/interrupt-controller/irq.h>:

      IRQ_TYPE_EDGE_RISING

      IRQ_TYPE_EDGE_FALLING

      IRQ_TYPE_EDGE_BOTH

 - clocks: Clock specifier (see clock bindings for details).

 - microchip,gpio-bank: Specifies which bank a controller owns.

 - gpio-ranges: Interaction with the PINCTRL subsystem.

Example:

/* PORTA */

gpio0: gpio0@1f860000 {

	compatible = "microchip,pic32mzda-gpio";

	reg = <0x1f860000 0x100>;

	interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;

	#gpio-cells = <2>;

	gpio-controller;

	interrupt-controller;

	#interrupt-cells = <2>;

	clocks = <&PBCLK4>;

	microchip,gpio-bank = <0>;

	gpio-ranges = <&pic32_pinctrl 0 0 16>;

};

keys {

	...

	button@sw1 {

		label = "ESC";

		linux,code = <1>;

		gpios = <&gpio0 12 0>;

	};

};

  "allwinner,sun9i-a80-r-pinctrl"

  "allwinner,sun8i-a83t-pinctrl"

  "allwinner,sun8i-h3-pinctrl"

  "allwinner,sun8i-h3-r-pinctrl"

  "allwinner,sun50i-a64-pinctrl"

- reg: Should contain the register physical address and length for the

  pin controller.

Broadcom Northstar2 IOMUX Controller

The Northstar2 IOMUX controller supports group based mux configuration. There

are some individual pins that support modifying the pinconf parameters.

Required properties:

- compatible:

    Must be "brcm,ns2-pinmux"

- reg:

    Define the base and range of the I/O address space that contains the

    Northstar2 IOMUX and pin configuration registers.

Properties in sub nodes:

- function:

    The mux function to select

- groups:

    The list of groups to select with a given function

- pins:

    List of pin names to change configuration

The generic properties bias-disable, bias-pull-down, bias-pull-up,

drive-strength, slew-rate, input-enable, input-disable are supported

for some individual pins listed at the end.

For more details, refer to

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

For example:

	pinctrl: pinctrl@6501d130 {

		compatible = "brcm,ns2-pinmux";

		reg = <0x6501d130 0x08>,

		      <0x660a0028 0x04>,

		      <0x660009b0 0x40>;

		pinctrl-names = "default";

		pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;

		/* Select nand function */

		nand_sel: nand_sel {

			function = "nand";

			groups = "nand_grp";

		};

		/* Pull up the uart3 rx pin */

		uart3_rx: uart3_rx {

			pins = "uart3_sin";

			bias-pull-up;

		};

		/* Set the drive strength of sdio d4 pin */

		sdio0_d4: sdio0_d4 {

			pins = "sdio0_data4";

			drive-strength = <8>;

		};

	};

List of supported functions and groups in Northstar2:

"nand": "nand_grp"

"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",

	"nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",

	"nor_addr_12_15_grp"

"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",

	"gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",

	"gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",

	"gpio_28_29_grp", "gpio_30_31_grp"

"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",

	"pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"

"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"

"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",

	"uart1_rts_cts_grp", "uart1_in_out_grp"

"uart2": "uart2_rts_cts_grp"

"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"

List of pins that support pinconf parameters:

"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",

"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",

"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",

"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",

"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",

"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",

"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",

"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",

"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",

"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",

"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",

"usb2_overcurrent", "sata_led1", "sata_led0"

* Microchip PIC32 Pin Controller

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and

../interrupt-controller/interrupts.txt for generic information regarding

pin controller, GPIO, and interrupt bindings.

PIC32 'pin configuration node' is a node of a group of pins which can be

used for a specific device or function. This node represents configuraions of

pins, optional function, and optional mux related configuration.

Required properties for pin controller node:

 - compatible: "microchip,pic32mada-pinctrl"

 - reg: Address range of the pinctrl registers.

 - clocks: Clock specifier (see clock bindings for details)

Required properties for pin configuration sub-nodes:

 - pins: List of pins to which the configuration applies.

Optional properties for pin configuration sub-nodes:

----------------------------------------------------

 - function: Mux function for the specified pins.

 - bias-pull-up: Enable weak pull-up.

 - bias-pull-down: Enable weak pull-down.

 - input-enable: Set the pin as an input.

 - output-low: Set the pin as an output level low.

 - output-high: Set the pin as an output level high.

 - microchip,digital: Enable digital I/O.

 - microchip,analog: Enable analog I/O.

Example:

pic32_pinctrl: pinctrl@1f801400{

	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "microchip,pic32mzda-pinctrl";

	reg = <0x1f801400 0x400>;

	clocks = <&PBCLK1>;

	pinctrl_uart2: pinctrl_uart2 {

		uart2-tx {

			pins = "G9";

			function = "U2TX";

			microchip,digital;

			output-low;

		};

		uart2-rx {

			pins = "B0";

			function = "U2RX";

			microchip,digital;

			input-enable;

		};

	};

};

uart2: serial@1f822200 {

	compatible = "microchip,pic32mzda-uart";

	reg = <0x1f822200 0x50>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

};

 - input-schmitt-disable

 - slew-rate

NXP specific properties:

 - nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller

			    irq number 0 to 7. See example below.

Not all pins support all properties so either refer to the NXP 1850/4350

user manual or the pin table in the pinctrl-lpc18xx driver for supported

pin properties.

			bias-disable;

		};

	};

	gpio_joystick_pins: gpio-joystick-pins {

		gpio_joystick_1_cfg {

			pins =  "p9_0";

			function = "gpio";

			nxp,gpio-pin-interrupt = <0>;

			input-enable;

			bias-disable;

		};

	};

};