Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net (5ca11440) · Commits · 戴 / test

Documentation/virtual/kvm/api.txt

+46 −0

Original line number	Diff line number	Diff line
		@@ -3403,6 +3403,52 @@ invalid, if invalid pages are written to (e.g. after the end of memory)
		or if no page table is present for the addresses (e.g. when using
		hugepages).

		4.108 KVM_PPC_GET_CPU_CHAR

		Capability: KVM_CAP_PPC_GET_CPU_CHAR
		Architectures: powerpc
		Type: vm ioctl
		Parameters: struct kvm_ppc_cpu_char (out)
		Returns: 0 on successful completion
		-EFAULT if struct kvm_ppc_cpu_char cannot be written

		This ioctl gives userspace information about certain characteristics
		of the CPU relating to speculative execution of instructions and
		possible information leakage resulting from speculative execution (see
		CVE-2017-5715, CVE-2017-5753 and CVE-2017-5754). The information is
		returned in struct kvm_ppc_cpu_char, which looks like this:

		struct kvm_ppc_cpu_char {
		__u64 character; /* characteristics of the CPU */
		__u64 behaviour; /* recommended software behaviour */
		__u64 character_mask; /* valid bits in character */
		__u64 behaviour_mask; /* valid bits in behaviour */
		};

		For extensibility, the character_mask and behaviour_mask fields
		indicate which bits of character and behaviour have been filled in by
		the kernel. If the set of defined bits is extended in future then
		userspace will be able to tell whether it is running on a kernel that
		knows about the new bits.

		The character field describes attributes of the CPU which can help
		with preventing inadvertent information disclosure - specifically,
		whether there is an instruction to flash-invalidate the L1 data cache
		(ori 30,30,0 or mtspr SPRN_TRIG2,rN), whether the L1 data cache is set
		to a mode where entries can only be used by the thread that created
		them, whether the bcctr[l] instruction prevents speculation, and
		whether a speculation barrier instruction (ori 31,31,0) is provided.

		The behaviour field describes actions that software should take to
		prevent inadvertent information disclosure, and thus describes which
		vulnerabilities the hardware is subject to; specifically whether the
		L1 data cache should be flushed when returning to user mode from the
		kernel, and whether a speculation barrier should be placed between an
		array bounds check and the array access.

		These fields use the same bit definitions as the new
		H_GET_CPU_CHARACTERISTICS hypercall.

		5. The kvm_run structure
		------------------------

Documentation/x86/pti.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -78,7 +78,7 @@ this protection comes at a cost:
		non-PTI SYSCALL entry code, so requires mapping fewer
		things into the userspace page tables. The downside is
		that stacks must be switched at entry time.
		d. Global pages are disabled for all kernel structures not
		c. Global pages are disabled for all kernel structures not
		mapped into both kernel and userspace page tables. This
		feature of the MMU allows different processes to share TLB
		entries mapping the kernel. Losing the feature means more

MAINTAINERS

+1 −0

Original line number	Diff line number	Diff line
		@@ -9102,6 +9102,7 @@ F: drivers/usb/image/microtek.*

		MIPS
		M: Ralf Baechle <ralf@linux-mips.org>
		M: James Hogan <jhogan@kernel.org>
		L: linux-mips@linux-mips.org
		W: http://www.linux-mips.org/
		T: git git://git.linux-mips.org/pub/scm/ralf/linux.git

Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -2,7 +2,7 @@
		VERSION = 4
		PATCHLEVEL = 15
		SUBLEVEL = 0
		EXTRAVERSION = -rc8
		EXTRAVERSION = -rc9
		NAME = Fearless Coyote

		# DOCUMENTATION

arch/alpha/kernel/sys_sio.c

+29 −6

Original line number	Diff line number	Diff line
		@@ -102,6 +102,15 @@ sio_pci_route(void)
		alpha_mv.sys.sio.route_tab);
		}

		static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
		{
		if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
		(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
		return false;

		return true;
		}

		static unsigned int __init
		sio_collect_irq_levels(void)
		{
		@@ -110,8 +119,7 @@ sio_collect_irq_levels(void)

		/* Iterate through the devices, collecting IRQ levels. */
		for_each_pci_dev(dev) {
		if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
		(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
		if (!sio_pci_dev_irq_needs_level(dev))
		continue;

		if (dev->irq)
		@@ -120,8 +128,7 @@ sio_collect_irq_levels(void)
		return level_bits;
		}

		static void __init
		sio_fixup_irq_levels(unsigned int level_bits)
		static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
		{
		unsigned int old_level_bits;

		@@ -139,12 +146,21 @@ sio_fixup_irq_levels(unsigned int level_bits)
		*/
		old_level_bits = inb(0x4d0) \| (inb(0x4d1) << 8);

		level_bits \|= (old_level_bits & 0x71ff);
		if (reset)
		old_level_bits &= 0x71ff;

		level_bits \|= old_level_bits;

		outb((level_bits >> 0) & 0xff, 0x4d0);
		outb((level_bits >> 8) & 0xff, 0x4d1);
		}

		static inline void
		sio_fixup_irq_levels(unsigned int level_bits)
		{
		__sio_fixup_irq_levels(level_bits, true);
		}

		static inline int
		noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
		{
		@@ -181,7 +197,14 @@ noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
		const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
		int irq = COMMON_TABLE_LOOKUP, tmp;
		tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
		return irq >= 0 ? tmp : -1;

		irq = irq >= 0 ? tmp : -1;

		/* Fixup IRQ level if an actual IRQ mapping is detected */
		if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
		__sio_fixup_irq_levels(1 << irq, false);

		return irq;
		}

		static inline int

Admin message