usb: musb: drop unneeded musb_debug trickery (5c8a86e1) · Commits · 戴 / test

drivers/usb/musb/Kconfig

+0 −8

Original line number	Original line	Diff line number	Diff line
	@@ -176,11 +176,3 @@ config USB_TUSB_OMAP_DMA
	help		help
	Enable DMA transfers on TUSB 6010 when OMAP DMA is available.		Enable DMA transfers on TUSB 6010 when OMAP DMA is available.

	config USB_MUSB_DEBUG
	depends on USB_MUSB_HDRC
	bool "Enable debugging messages"
	default n
	help
	This enables musb debugging. To set the logging level use the debug
	module parameter. Starting at level 3, per-transfer (urb, usb_request,
	packet, or dma transfer) tracing may kick in.

drivers/usb/musb/Makefile

+0 −2

Original line number	Original line	Diff line number	Diff line
	@@ -2,8 +2,6 @@
	# for USB OTG silicon based on Mentor Graphics INVENTRA designs		# for USB OTG silicon based on Mentor Graphics INVENTRA designs
	#		#

	ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG

	obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o		obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o

	musb_hdrc-y := musb_core.o		musb_hdrc-y := musb_core.o

drivers/usb/musb/am35x.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -151,7 +151,7 @@ static void otg_timer(unsigned long _musb)
	* status change events (from the transceiver) otherwise.		* status change events (from the transceiver) otherwise.
	*/		*/
	devctl = musb_readb(mregs, MUSB_DEVCTL);		devctl = musb_readb(mregs, MUSB_DEVCTL);
	DBG(7, "Poll devctl %02x (%s)\n", devctl,		dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
	otg_state_string(musb->xceiv->state));		otg_state_string(musb->xceiv->state));

	spin_lock_irqsave(&musb->lock, flags);		spin_lock_irqsave(&musb->lock, flags);
	@@ -203,7 +203,7 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
	/* Never idle if active, or when VBUS timeout is not set as host */		/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active \|\| (musb->a_wait_bcon == 0 &&		if (musb->is_active \|\| (musb->a_wait_bcon == 0 &&
	musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {		musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
	DBG(4, "%s active, deleting timer\n",		dev_dbg(musb->controller, "%s active, deleting timer\n",
	otg_state_string(musb->xceiv->state));		otg_state_string(musb->xceiv->state));
	del_timer(&otg_workaround);		del_timer(&otg_workaround);
	last_timer = jiffies;		last_timer = jiffies;
	@@ -211,12 +211,12 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
	}		}

	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {		if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
	DBG(4, "Longer idle timer already pending, ignoring...\n");		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
	return;		return;
	}		}
	last_timer = timeout;		last_timer = timeout;

	DBG(4, "%s inactive, starting idle timer for %u ms\n",		dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
	otg_state_string(musb->xceiv->state),		otg_state_string(musb->xceiv->state),
	jiffies_to_msecs(timeout - jiffies));		jiffies_to_msecs(timeout - jiffies));
	mod_timer(&otg_workaround, timeout);		mod_timer(&otg_workaround, timeout);
	@@ -305,7 +305,7 @@ static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
	}		}

	/* NOTE: this must complete power-on within 100 ms. */		/* NOTE: this must complete power-on within 100 ms. */
	DBG(2, "VBUS %s (%s)%s, devctl %02x\n",		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
	drvvbus ? "on" : "off",		drvvbus ? "on" : "off",
	otg_state_string(musb->xceiv->state),		otg_state_string(musb->xceiv->state),
	err ? " ERROR" : "",		err ? " ERROR" : "",

drivers/usb/musb/blackfin.c

+6 −5

Original line number	Original line	Diff line number	Diff line
	@@ -43,7 +43,7 @@ void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)

	musb_writew(epio, MUSB_TXCOUNT, len);		musb_writew(epio, MUSB_TXCOUNT, len);

	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",		dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
	hw_ep->epnum, fifo, len, src, epio);		hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);		dump_fifo_data(src, len);
	@@ -154,7 +154,7 @@ void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);		*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	}		}
	}		}
	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",		dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
	'R', hw_ep->epnum, fifo, len, dst);		'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);		dump_fifo_data(dst, len);
	@@ -279,13 +279,14 @@ static void musb_conn_timer_handler(unsigned long _musb)
	}		}
	break;		break;
	default:		default:
	DBG(1, "%s state not handled\n",		dev_dbg(musb->controller, "%s state not handled\n",
	otg_state_string(musb->xceiv->state));		otg_state_string(musb->xceiv->state));
	break;		break;
	}		}
	spin_unlock_irqrestore(&musb->lock, flags);		spin_unlock_irqrestore(&musb->lock, flags);

	DBG(4, "state is %s\n", otg_state_string(musb->xceiv->state));		dev_dbg(musb->controller, "state is %s\n",
			otg_state_string(musb->xceiv->state));
	}		}

	static void bfin_musb_enable(struct musb *musb)		static void bfin_musb_enable(struct musb *musb)
	@@ -307,7 +308,7 @@ static void bfin_musb_set_vbus(struct musb *musb, int is_on)
	value = !value;		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);		gpio_set_value(musb->config->gpio_vrsel, value);

	DBG(1, "VBUS %s, devctl %02x "		dev_dbg(musb->controller, "VBUS %s, devctl %02x "
	/* otg %3x conf %08x prcm %08x */ "\n",		/* otg %3x conf %08x prcm %08x */ "\n",
	otg_state_string(musb->xceiv->state),		otg_state_string(musb->xceiv->state),
	musb_readb(musb->mregs, MUSB_DEVCTL));		musb_readb(musb->mregs, MUSB_DEVCTL));

drivers/usb/musb/cppi_dma.c

+17 −17

Original line number	Original line	Diff line number	Diff line
	@@ -236,7 +236,7 @@ static int cppi_controller_stop(struct dma_controller *c)
	musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,		musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
	DAVINCI_DMA_ALL_CHANNELS_ENABLE);		DAVINCI_DMA_ALL_CHANNELS_ENABLE);

	DBG(1, "Tearing down RX and TX Channels\n");		dev_dbg(musb->controller, "Tearing down RX and TX Channels\n");
	for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {		for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
	/* FIXME restructure of txdma to use bds like rxdma */		/* FIXME restructure of txdma to use bds like rxdma */
	controller->tx[i].last_processed = NULL;		controller->tx[i].last_processed = NULL;
	@@ -301,13 +301,13 @@ cppi_channel_allocate(struct dma_controller *c,
	*/		*/
	if (transmit) {		if (transmit) {
	if (index >= ARRAY_SIZE(controller->tx)) {		if (index >= ARRAY_SIZE(controller->tx)) {
	DBG(1, "no %cX%d CPPI channel\n", 'T', index);		dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index);
	return NULL;		return NULL;
	}		}
	cppi_ch = controller->tx + index;		cppi_ch = controller->tx + index;
	} else {		} else {
	if (index >= ARRAY_SIZE(controller->rx)) {		if (index >= ARRAY_SIZE(controller->rx)) {
	DBG(1, "no %cX%d CPPI channel\n", 'R', index);		dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index);
	return NULL;		return NULL;
	}		}
	cppi_ch = controller->rx + index;		cppi_ch = controller->rx + index;
	@@ -318,13 +318,13 @@ cppi_channel_allocate(struct dma_controller *c,
	* with the other DMA engine too		* with the other DMA engine too
	*/		*/
	if (cppi_ch->hw_ep)		if (cppi_ch->hw_ep)
	DBG(1, "re-allocating DMA%d %cX channel %p\n",		dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n",
	index, transmit ? 'T' : 'R', cppi_ch);		index, transmit ? 'T' : 'R', cppi_ch);
	cppi_ch->hw_ep = ep;		cppi_ch->hw_ep = ep;
	cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;		cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
	cppi_ch->channel.max_len = 0x7fffffff;		cppi_ch->channel.max_len = 0x7fffffff;

	DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');		dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
	return &cppi_ch->channel;		return &cppi_ch->channel;
	}		}

	@@ -339,7 +339,7 @@ static void cppi_channel_release(struct dma_channel *channel)
	c = container_of(channel, struct cppi_channel, channel);		c = container_of(channel, struct cppi_channel, channel);
	tibase = c->controller->tibase;		tibase = c->controller->tibase;
	if (!c->hw_ep)		if (!c->hw_ep)
	DBG(1, "releasing idle DMA channel %p\n", c);		dev_dbg(musb->controller, "releasing idle DMA channel %p\n", c);
	else if (!c->transmit)		else if (!c->transmit)
	core_rxirq_enable(tibase, c->index + 1);		core_rxirq_enable(tibase, c->index + 1);

	@@ -597,7 +597,7 @@ cppi_next_tx_segment(struct musb musb, struct cppi_channel tx)
	length = min(n_bds * maxpacket, length);		length = min(n_bds * maxpacket, length);
	}		}

	DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",		dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
	tx->index,		tx->index,
	maxpacket,		maxpacket,
	rndis ? "rndis" : "transparent",		rndis ? "rndis" : "transparent",
	@@ -654,7 +654,7 @@ cppi_next_tx_segment(struct musb musb, struct cppi_channel tx)
	bd->hw_options \|= CPPI_ZERO_SET;		bd->hw_options \|= CPPI_ZERO_SET;
	}		}

	DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",		dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
	bd, bd->hw_next, bd->hw_bufp,		bd, bd->hw_next, bd->hw_bufp,
	bd->hw_off_len, bd->hw_options);		bd->hw_off_len, bd->hw_options);

	@@ -819,7 +819,7 @@ cppi_next_rx_segment(struct musb musb, struct cppi_channel rx, int onepacket)

	length = min(n_bds * maxpacket, length);		length = min(n_bds * maxpacket, length);

	DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "		dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
	"dma 0x%llx len %u %u/%u\n",		"dma 0x%llx len %u %u/%u\n",
	rx->index, maxpacket,		rx->index, maxpacket,
	onepacket		onepacket
	@@ -936,7 +936,7 @@ cppi_next_rx_segment(struct musb musb, struct cppi_channel rx, int onepacket)
	DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))		DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
	& 0xffff;		& 0xffff;
	if (i < (2 + n_bds)) {		if (i < (2 + n_bds)) {
	DBG(2, "bufcnt%d underrun - %d (for %d)\n",		dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n",
	rx->index, i, n_bds);		rx->index, i, n_bds);
	musb_writel(tibase,		musb_writel(tibase,
	DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),		DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
	@@ -985,7 +985,7 @@ static int cppi_channel_program(struct dma_channel *ch,
	/* WARN_ON(1); */		/* WARN_ON(1); */
	break;		break;
	case MUSB_DMA_STATUS_UNKNOWN:		case MUSB_DMA_STATUS_UNKNOWN:
	DBG(1, "%cX DMA%d not allocated!\n",		dev_dbg(musb->controller, "%cX DMA%d not allocated!\n",
	cppi_ch->transmit ? 'T' : 'R',		cppi_ch->transmit ? 'T' : 'R',
	cppi_ch->index);		cppi_ch->index);
	/* FALLTHROUGH */		/* FALLTHROUGH */
	@@ -1040,7 +1040,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
	if (!completed && (bd->hw_options & CPPI_OWN_SET))		if (!completed && (bd->hw_options & CPPI_OWN_SET))
	break;		break;

	DBG(5, "C/RXBD %llx: nxt %08x buf %08x "		dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x "
	"off.len %08x opt.len %08x (%d)\n",		"off.len %08x opt.len %08x (%d)\n",
	(unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,		(unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
	bd->hw_off_len, bd->hw_options,		bd->hw_off_len, bd->hw_options,
	@@ -1062,7 +1062,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
	* CPPI ignores those BDs even though OWN is still set.		* CPPI ignores those BDs even though OWN is still set.
	*/		*/
	completed = true;		completed = true;
	DBG(3, "rx short %d/%d (%d)\n",		dev_dbg(musb->controller, "rx short %d/%d (%d)\n",
	len, bd->buflen,		len, bd->buflen,
	rx->channel.actual_len);		rx->channel.actual_len);
	}		}
	@@ -1112,7 +1112,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
	musb_ep_select(cppi->mregs, rx->index + 1);		musb_ep_select(cppi->mregs, rx->index + 1);
	csr = musb_readw(regs, MUSB_RXCSR);		csr = musb_readw(regs, MUSB_RXCSR);
	if (csr & MUSB_RXCSR_DMAENAB) {		if (csr & MUSB_RXCSR_DMAENAB) {
	DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n",		dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
	rx->index,		rx->index,
	rx->head, rx->tail,		rx->head, rx->tail,
	rx->last_processed		rx->last_processed
	@@ -1175,7 +1175,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
	return IRQ_NONE;		return IRQ_NONE;
	}		}

	DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);		dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);

	/* process TX channels */		/* process TX channels */
	for (index = 0; tx; tx = tx >> 1, index++) {		for (index = 0; tx; tx = tx >> 1, index++) {
	@@ -1203,7 +1203,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
	* that needs to be acknowledged.		* that needs to be acknowledged.
	*/		*/
	if (NULL == bd) {		if (NULL == bd) {
	DBG(1, "null BD\n");		dev_dbg(musb->controller, "null BD\n");
	musb_writel(&tx_ram->tx_complete, 0, 0);		musb_writel(&tx_ram->tx_complete, 0, 0);
	continue;		continue;
	}		}
	@@ -1218,7 +1218,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
	if (bd->hw_options & CPPI_OWN_SET)		if (bd->hw_options & CPPI_OWN_SET)
	break;		break;

	DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n",		dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n",
	bd, bd->hw_next, bd->hw_bufp,		bd, bd->hw_next, bd->hw_bufp,
	bd->hw_off_len, bd->hw_options);		bd->hw_off_len, bd->hw_options);

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