drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings (5c583018) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+23 −0

Original line number	Diff line number	Diff line
		@@ -32,6 +32,8 @@
		#include "vega10/DC/dce_12_0_offset.h"
		#include "vega10/DC/dce_12_0_sh_mask.h"
		#include "vega10/vega10_enum.h"
		#include "vega10/MMHUB/mmhub_1_0_offset.h"
		#include "vega10/ATHUB/athub_1_0_offset.h"

		#include "soc15_common.h"

		@@ -71,6 +73,18 @@ static const u32 golden_settings_vega10_hdp[] =
		0xf6e, 0x0fffffff, 0x00000000,
		};

		static const u32 golden_settings_mmhub_1_0_0[] =
		{
		SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
		SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
		};

		static const u32 golden_settings_athub_1_0_0[] =
		{
		SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
		SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
		};

		static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
		struct amdgpu_irq_src *src,
		unsigned type,
		@@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
		{
		switch (adev->asic_type) {
		case CHIP_VEGA10:
		amdgpu_program_register_sequence(adev,
		golden_settings_mmhub_1_0_0,
		(const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
		amdgpu_program_register_sequence(adev,
		golden_settings_athub_1_0_0,
		(const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
		break;
		case CHIP_RAVEN:
		amdgpu_program_register_sequence(adev,
		golden_settings_athub_1_0_0,
		(const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
		break;
		default:
		break;