Commit 5c33f8b2 authored by Matt Redfearn's avatar Matt Redfearn Committed by Ralf Baechle
Browse files

MIPS: Add definitions of SegCtl registers and use them 



The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of
these registers and use them rather than constants

Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13290/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent dd317403

arch/mips/include/asm/mach-malta/kernel-entry-init.h

+3 −3
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ 
		(0 << MIPS_SEGCFG_PA_SHIFT) |				\

		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)

	or	t0, t2

	mtc0	t0, $5, 2

	mtc0	t0, CP0_SEGCTL0



	/* SegCtl1 */

	li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |	\
@@ -67,7 +67,7 @@ 
		(0 << MIPS_SEGCFG_PA_SHIFT) |				\

		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)

	ins	t0, t1, 16, 3

	mtc0	t0, $5, 3

	mtc0	t0, CP0_SEGCTL1



	/* SegCtl2 */

	li	t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |	\
@@ -77,7 +77,7 @@ 
		(4 << MIPS_SEGCFG_PA_SHIFT) |				\

		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)

	or	t0, t2

	mtc0	t0, $5, 4

	mtc0	t0, CP0_SEGCTL2



	jal	mips_ihb

	mfc0    t0, $16, 5

arch/mips/include/asm/mipsregs.h

+3 −0
Original line number Diff line number Diff line
@@ -48,6 +48,9 @@ 
#define CP0_CONF $3

#define CP0_CONTEXT $4

#define CP0_PAGEMASK $5

#define CP0_SEGCTL0 $5, 2

#define CP0_SEGCTL1 $5, 3

#define CP0_SEGCTL2 $5, 4

#define CP0_WIRED $6

#define CP0_INFO $7

#define CP0_HWRENA $7, 0

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