drm/i915/icl: WaGAPZPriorityScheme (5bcebe76) · Commits · 戴 / test

The default GAPZ arbitrer priority value at power-on has been found to be incorrect. v2: Now renamed to Wa_1405543622 v3: Rebased on top of the WA refactoring v4: Added HSDES reference number (Mika) v5: - Rebased - C, not lisp (Chris) References: HSDES#1405543622 Signed-off-by:

Oscar Mateo <oscar.mateo@intel.com> Reviewed-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-4-git-send-email-oscar.mateo@intel.com

drivers/gpu/drm/i915/i915_reg.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -8252,6 +8252,7 @@ enum {

		#define GEN8_GARBCNTL _MMIO(0xB004)
		#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
		#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)

		#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
		#define DFR_DISABLE (1 << 9)

drivers/gpu/drm/i915/intel_workarounds.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -699,6 +699,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
		/* WaPipelineFlushCoherentLines:icl */
		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) \|
		GEN8_LQSC_FLUSH_COHERENT_LINES);

		/* Wa_1405543622:icl
		* Formerly known as WaGAPZPriorityScheme
		*/
		I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) \|
		GEN11_ARBITRATION_PRIO_ORDER_MASK);
		}

		void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)

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