Commit 5bc7c33c authored by Brian Norris's avatar Brian Norris Committed by David Woodhouse
Browse files

mtd: nand: reintroduce NAND_NO_READRDY as NAND_NEED_READRDY 



This partially reverts commit 1696e6bc
("mtd: nand: kill NAND_NO_READRDY").

In that patch I overlooked a few things.

The original documentation for NAND_NO_READRDY included "True for all
large page devices, as they do not support autoincrement." I was
conflating "not support autoincrement" with the NAND_NO_AUTOINCR option,
which was in fact doing nothing. So, when I dropped NAND_NO_AUTOINCR, I
concluded that I then could harmlessly drop NAND_NO_READRDY. But of
course the fact the NAND_NO_AUTOINCR was doing nothing didn't mean
NAND_NO_READRDY was doing nothing...

So, NAND_NO_READRDY is re-introduced as NAND_NEED_READRDY and applied
only to those few remaining small-page NAND which needed it in the first
place.

Cc: stable@kernel.org [3.5+]
Reported-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Tested-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent 91d542f4

drivers/mtd/nand/nand_base.c

+16 −0
Original line number Diff line number Diff line
@@ -1523,6 +1523,14 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, 
					oobreadlen -= toread;

				}

			}



			if (chip->options & NAND_NEED_READRDY) {

				/* Apply delay or wait for ready/busy pin */

				if (!chip->dev_ready)

					udelay(chip->chip_delay);

				else

					nand_wait_ready(mtd);

			}

		} else {

			memcpy(buf, chip->buffers->databuf + col, bytes);

			buf += bytes;
@@ -1787,6 +1795,14 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, 
		len = min(len, readlen);

		buf = nand_transfer_oob(chip, buf, ops, len);



		if (chip->options & NAND_NEED_READRDY) {

			/* Apply delay or wait for ready/busy pin */

			if (!chip->dev_ready)

				udelay(chip->chip_delay);

			else

				nand_wait_ready(mtd);

		}



		readlen -= len;

		if (!readlen)

			break;

drivers/mtd/nand/nand_ids.c

+41 −39
Original line number Diff line number Diff line
@@ -22,49 +22,51 @@ 
*	512	512 Byte page size

*/

struct nand_flash_dev nand_flash_ids[] = {

#define SP_OPTIONS NAND_NEED_READRDY

#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)



#ifdef CONFIG_MTD_NAND_MUSEUM_IDS

	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, 0},

	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, 0},

	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, 0},

	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, 0},

	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, 0},

	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, 0},

	{"NAND 4MiB 3,3V 8-bit",	0xd5, 512, 4, 0x2000, 0},

	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, 0},

	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, 0},

	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, 0},



	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, 0},

	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, 0},

	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},

	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},

	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, SP_OPTIONS},

	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, SP_OPTIONS},

	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, SP_OPTIONS},

	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, SP_OPTIONS},

	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, SP_OPTIONS},

	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, SP_OPTIONS},

	{"NAND 4MiB 3,3V 8-bit",	0xd5, 512, 4, 0x2000, SP_OPTIONS},

	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, SP_OPTIONS},

	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, SP_OPTIONS},

	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, SP_OPTIONS},



	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, SP_OPTIONS},

	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, SP_OPTIONS},

	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, SP_OPTIONS16},

	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, SP_OPTIONS16},

#endif



	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, 0},

	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, 0},

	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},



	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, 0},

	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, 0},

	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},



	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, 0},

	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, 0},

	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},



	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, 0},

	{"NAND 128MiB 1,8V 8-bit",	0x39, 512, 128, 0x4000, 0},

	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, 0},

	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 128MiB 1,8V 16-bit",	0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},

	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},



	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},

	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, SP_OPTIONS},

	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, SP_OPTIONS},

	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, SP_OPTIONS16},

	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, SP_OPTIONS16},



	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, SP_OPTIONS},

	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, SP_OPTIONS},

	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, SP_OPTIONS16},

	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, SP_OPTIONS16},



	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, SP_OPTIONS},

	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, SP_OPTIONS},

	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, SP_OPTIONS16},

	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, SP_OPTIONS16},



	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, SP_OPTIONS},

	{"NAND 128MiB 1,8V 8-bit",	0x39, 512, 128, 0x4000, SP_OPTIONS},

	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, SP_OPTIONS},

	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, SP_OPTIONS16},

	{"NAND 128MiB 1,8V 16-bit",	0x49, 512, 128, 0x4000, SP_OPTIONS16},

	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, SP_OPTIONS16},

	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, SP_OPTIONS16},



	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, SP_OPTIONS},



	/*

	 * These are the new chips with large page size. The pagesize and the

include/linux/mtd/nand.h

+7 −0
Original line number Diff line number Diff line
@@ -187,6 +187,13 @@ typedef enum { 
 * This happens with the Renesas AG-AND chips, possibly others.

 */

#define BBT_AUTO_REFRESH	0x00000080

/*

 * Chip requires ready check on read (for auto-incremented sequential read).

 * True only for small page devices; large page devices do not support

 * autoincrement.

 */

#define NAND_NEED_READRDY	0x00000100



/* Chip does not allow subpage writes */

#define NAND_NO_SUBPAGE_WRITE	0x00000200

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