Commit 5bc5d99f authored by Thierry Reding's avatar Thierry Reding
Browse files

pwm: iqs620a: Use 64-bit division 



The PWM framework is going to change the PWM period and duty cycles to
be 64-bit unsigned integers. To avoid build errors on platforms that do
not natively support 64-bit division, use explicity 64-bit division.

Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 1689dcd4

drivers/pwm/pwm-iqs620a.c

+4 −3
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 
{

	struct iqs620_pwm_private *iqs620_pwm;

	struct iqs62x_core *iqs62x;

	int duty_scale, ret;

	u64 duty_scale;

	int ret;



	if (state->polarity != PWM_POLARITY_NORMAL)

		return -ENOTSUPP;
@@ -69,7 +70,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 
	 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to

	 * allow an external pull-down resistor to hold the GPIO3/LTX pin low.

	 */

	duty_scale = state->duty_cycle * 256 / IQS620_PWM_PERIOD_NS;

	duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);



	mutex_lock(&iqs620_pwm->lock);
@@ -81,7 +82,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 
	}



	if (duty_scale) {

		u8 duty_val = min(duty_scale - 1, 0xFF);

		u8 duty_val = min_t(u64, duty_scale - 1, 0xff);



		ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,

				   duty_val);

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