drm/amd/powerplay: refine dmesg info under powerplay. (5bbc5c64) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+6 −7

Original line number	Diff line number	Diff line
		@@ -557,9 +557,8 @@ uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, u
		return vddci_table->entries[i].value;
		}

		PP_ASSERT_WITH_CODE(false,
		"VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
		return vddci_table->entries[i-1].value);
		pr_debug("vddci is larger than max value in vddci_table\n");
		return vddci_table->entries[i-1].value;
		}

		int phm_find_boot_level(void *table,
		@@ -597,10 +596,10 @@ int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
		break;
		}

		PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
		"Can't find requested voltage id in vdd_dep_on_sclk table!",
		if (entryId >= table_info->vdd_dep_on_sclk->count) {
		pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n");
		return -EINVAL;
		);
		}

		*sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;

+1 −1

Original line number	Diff line number	Diff line
		@@ -4162,7 +4162,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
		pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
		}
		} else {
		pr_info("Cannot find requested DCEFCLK!");
		pr_debug("Cannot find requested DCEFCLK!");
		}

		if (min_clocks.memoryClock != 0) {