x86, amd: Disable GartTlbWlkErr when BIOS forgets it

#define MSR_IA32_MC0_ADDR		0x00000402

#define MSR_IA32_MC0_MISC		0x00000403

#define MSR_AMD64_MC0_MASK		0xc0010044

#define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))

#define MSR_IA32_MCx_STATUS(x)		(MSR_IA32_MC0_STATUS + 4*(x))

#define MSR_IA32_MCx_ADDR(x)		(MSR_IA32_MC0_ADDR + 4*(x))

#define MSR_IA32_MCx_MISC(x)		(MSR_IA32_MC0_MISC + 4*(x))

#define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))

/* These are consecutive and not in the normal 4er MCE bank block */

#define MSR_IA32_MC0_CTL2		0x00000280

#define MSR_IA32_MCx_CTL2(x)		(MSR_IA32_MC0_CTL2 + (x))

	/* As a rule processors have APIC timer running in deep C states */

	if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400))

		set_cpu_cap(c, X86_FEATURE_ARAT);

	/*

	 * Disable GART TLB Walk Errors on Fam10h. We do this here

	 * because this is always needed when GART is enabled, even in a

	 * kernel which has no MCE support built in.

	 */

	if (c->x86 == 0x10) {

		/*

		 * BIOS should disable GartTlbWlk Errors themself. If

		 * it doesn't do it here as suggested by the BKDG.

		 *

		 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012

		 */

		u64 mask;

		rdmsrl(MSR_AMD64_MCx_MASK(4), mask);

		mask |= (1 << 10);

		wrmsrl(MSR_AMD64_MCx_MASK(4), mask);

	}

}

#ifdef CONFIG_X86_32