drm/amd/powerplay: add function set_watermarks_table function for navi10 (5bbb0994) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+61 −0

Original line number	Diff line number	Diff line
		@@ -1110,6 +1110,66 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
		return 0;
		}

		static int navi10_set_watermarks_table(struct smu_context *smu,
		void *watermarks, struct
		dm_pp_wm_sets_with_clock_ranges_soc15
		*clock_ranges)
		{
		int i;
		Watermarks_t *table = watermarks;

		if (!table \|\| !clock_ranges)
		return -EINVAL;

		if (clock_ranges->num_wm_dmif_sets > 4 \|\|
		clock_ranges->num_wm_mcif_sets > 4)
		return -EINVAL;

		for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
		table->WatermarkRow[1][i].MinClock =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
		1000));
		table->WatermarkRow[1][i].MaxClock =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
		1000));
		table->WatermarkRow[1][i].MinUclk =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
		1000));
		table->WatermarkRow[1][i].MaxUclk =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
		1000));
		table->WatermarkRow[1][i].WmSetting = (uint8_t)
		clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
		}

		for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
		table->WatermarkRow[0][i].MinClock =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
		1000));
		table->WatermarkRow[0][i].MaxClock =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
		1000));
		table->WatermarkRow[0][i].MinUclk =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
		1000));
		table->WatermarkRow[0][i].MaxUclk =
		cpu_to_le16((uint16_t)
		(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
		1000));
		table->WatermarkRow[0][i].WmSetting = (uint8_t)
		clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
		}

		return 0;
		}

		static const struct pptable_funcs navi10_ppt_funcs = {
		.tables_init = navi10_tables_init,
		.alloc_dpm_context = navi10_allocate_dpm_context,
		@@ -1143,6 +1203,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
		.get_power_profile_mode = navi10_get_power_profile_mode,
		.set_power_profile_mode = navi10_set_power_profile_mode,
		.get_profiling_clk_mask = navi10_get_profiling_clk_mask,
		.set_watermarks_table = navi10_set_watermarks_table,
		};

		void navi10_set_ppt_funcs(struct smu_context *smu)

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