Commit 5bb7ff79 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 5033/1: Unbreak corgi_ssp by registering ssp drivers earlier.
  [ARM] Orion: clean up addr-map.c after window setting code purge
  [ARM] Orion: pass proper t_clk into mv643xx_eth
  [ARM] Orion: use mv643xx_eth driver mbus window handling
  [ARM] pxa: Fix RCSR handling
  [ARM] lubbock: fix compilation
  [ARM] 5032/1: Added cpufreq support for pxa27x CPU
  [ARM] 5031/1: Indentation correction in cpu-pxa.c.
  [ARM] 5028/1: pxafb: fix broken "backward compatibility way" in framebuffer
  [ARM] 4882/2: Correction for S3C2410 clkout generation
  [ARM] 5027/1: Fixed random memory corruption on pxa suspend cycle.
  [ARM] 5024/1: Fix some minor clk issues in the MMCI PL18x driver
  [ARM] 5023/1: Fix broken gpio interrupts on ep93xx
  ns9xxx: fix sparse warning
  ns9xxx: check for irq lockups
  ns9xxx: fix handle_prio_irq to unmask irqs with lower priority
parents 3e1b83ab 1f2ee649

arch/arm/mach-ep93xx/core.c

+1 −1
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) 
	const int port = gpio >> 3;

	const int port_mask = 1 << (gpio & 7);



	gpio_direction_output(gpio, gpio_get_value(gpio));

	gpio_direction_input(gpio);



	switch (type) {

	case IRQT_RISING:

arch/arm/mach-ns9xxx/irq.c

+15 −7
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static struct irq_chip ns9xxx_chip = { 
#if 0

#define handle_irq handle_level_irq

#else

void handle_prio_irq(unsigned int irq, struct irq_desc *desc)

static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)

{

	unsigned int cpu = smp_processor_id();

	struct irqaction *action;
@@ -70,27 +70,35 @@ void handle_prio_irq(unsigned int irq, struct irq_desc *desc) 


	spin_lock(&desc->lock);



	if (unlikely(desc->status & IRQ_INPROGRESS))

		goto out_unlock;

	BUG_ON(desc->status & IRQ_INPROGRESS);



	desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);

	kstat_cpu(cpu).irqs[irq]++;



	action = desc->action;

	if (unlikely(!action || (desc->status & IRQ_DISABLED)))

		goto out_unlock;

		goto out_mask;



	desc->status |= IRQ_INPROGRESS;

	spin_unlock(&desc->lock);



	action_ret = handle_IRQ_event(irq, action);



	/* XXX: There is no direct way to access noirqdebug, so check

	 * unconditionally for spurious irqs...

	 * Maybe this function should go to kernel/irq/chip.c? */

	note_interrupt(irq, desc, action_ret);



	spin_lock(&desc->lock);

	desc->status &= ~IRQ_INPROGRESS;

	if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)



	if (desc->status & IRQ_DISABLED)

out_mask:

		desc->chip->mask(irq);



	/* ack unconditionally to unmask lower prio irqs */

	desc->chip->ack(irq);



out_unlock:

	spin_unlock(&desc->lock);

}

#define handle_irq handle_prio_irq

arch/arm/mach-orion5x/addr-map.c

+3 −63
Original line number Diff line number Diff line
@@ -34,11 +34,7 @@ 
 * Non-CPU Masters address decoding --

 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR

 * banks only (the typical use case).

 * Setup access for each master to DDR is issued by common.c.

 *

 * Note: although orion_setbits() and orion_clrbits() are not atomic

 * no locking is necessary here since code in this file is only called

 * at boot time when there is no concurrency issues.

 * Setup access for each master to DDR is issued by platform device setup.

 */



/*
@@ -48,10 +44,6 @@ 
#define TARGET_DEV_BUS		1

#define TARGET_PCI		3

#define TARGET_PCIE		4

#define ATTR_DDR_CS(n)		(((n) ==0) ? 0xe :	\

				((n) == 1) ? 0xd :	\

				((n) == 2) ? 0xb :	\

				((n) == 3) ? 0x7 : 0xf)

#define ATTR_PCIE_MEM		0x59

#define ATTR_PCIE_IO		0x51

#define ATTR_PCIE_WA		0x79
@@ -61,17 +53,12 @@ 
#define ATTR_DEV_CS1		0x1d

#define ATTR_DEV_CS2		0x1b

#define ATTR_DEV_BOOT		0xf

#define WIN_EN			1



/*

 * Helpers to get DDR bank info

 */

#define DDR_BASE_CS(n)		ORION5X_DDR_REG(0x1500 + ((n) * 8))

#define DDR_SIZE_CS(n)		ORION5X_DDR_REG(0x1504 + ((n) * 8))

#define DDR_MAX_CS		4

#define DDR_REG_TO_SIZE(reg)	(((reg) | 0xffffff) + 1)

#define DDR_REG_TO_BASE(reg)	((reg) & 0xff000000)

#define DDR_BANK_EN		1

#define DDR_BASE_CS(n)		ORION5X_DDR_REG(0x1500 + ((n) << 3))

#define DDR_SIZE_CS(n)		ORION5X_DDR_REG(0x1504 + ((n) << 3))



/*

 * CPU Address Decode Windows registers
@@ -81,17 +68,6 @@ 
#define CPU_WIN_REMAP_LO(n)	ORION5X_BRIDGE_REG(0x008 | ((n) << 4))

#define CPU_WIN_REMAP_HI(n)	ORION5X_BRIDGE_REG(0x00c | ((n) << 4))



/*

 * Gigabit Ethernet Address Decode Windows registers

 */

#define ETH_WIN_BASE(win)	ORION5X_ETH_REG(0x200 + ((win) * 8))

#define ETH_WIN_SIZE(win)	ORION5X_ETH_REG(0x204 + ((win) * 8))

#define ETH_WIN_REMAP(win)	ORION5X_ETH_REG(0x280 + ((win) * 4))

#define ETH_WIN_EN		ORION5X_ETH_REG(0x290)

#define ETH_WIN_PROT		ORION5X_ETH_REG(0x294)

#define ETH_MAX_WIN		6

#define ETH_MAX_REMAP_WIN	4





struct mbus_dram_target_info orion5x_mbus_dram_info;
@@ -202,39 +178,3 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) 
{

	setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);

}
 


void __init orion5x_setup_eth_wins(void)

{

	int i;



	/*

	 * First, disable and clear windows

	 */

	for (i = 0; i < ETH_MAX_WIN; i++) {

		orion5x_write(ETH_WIN_BASE(i), 0);

		orion5x_write(ETH_WIN_SIZE(i), 0);

		orion5x_setbits(ETH_WIN_EN, 1 << i);

		orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));

		if (i < ETH_MAX_REMAP_WIN)

			orion5x_write(ETH_WIN_REMAP(i), 0);

	}



	/*

	 * Setup windows for DDR banks.

	 */

	for (i = 0; i < DDR_MAX_CS; i++) {

		u32 base, size;

		size = orion5x_read(DDR_SIZE_CS(i));

		base = orion5x_read(DDR_BASE_CS(i));

		if (size & DDR_BANK_EN) {

			base = DDR_REG_TO_BASE(base);

			size = DDR_REG_TO_SIZE(size);

			orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);

			orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |

					(ATTR_DDR_CS(i) << 8) |

					TARGET_DDR);

			orion5x_clrbits(ETH_WIN_EN, 1 << i);

			orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));

		}

	}

}

arch/arm/mach-orion5x/common.c

+8 −1
Original line number Diff line number Diff line
@@ -190,6 +190,11 @@ static struct platform_device orion5x_ehci1 = { 
 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)

 ****************************************************************************/



struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {

	.dram		= &orion5x_mbus_dram_info,

	.t_clk		= ORION5X_TCLK,

};



static struct resource orion5x_eth_shared_resources[] = {

	{

		.start	= ORION5X_ETH_PHYS_BASE + 0x2000,
@@ -201,6 +206,9 @@ static struct resource orion5x_eth_shared_resources[] = { 
static struct platform_device orion5x_eth_shared = {

	.name		= MV643XX_ETH_SHARED_NAME,

	.id		= 0,

	.dev		= {

		.platform_data	= &orion5x_eth_shared_data,

	},

	.num_resources	= 1,

	.resource	= orion5x_eth_shared_resources,

};
@@ -362,7 +370,6 @@ void __init orion5x_init(void) 
	 * Setup Orion address map

	 */

	orion5x_setup_cpu_mbus_bridge();

	orion5x_setup_eth_wins();



	/*

	 * Register devices.

arch/arm/mach-orion5x/common.h

+0 −1
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ void orion5x_setup_dev0_win(u32 base, u32 size); 
void orion5x_setup_dev1_win(u32 base, u32 size);

void orion5x_setup_dev2_win(u32 base, u32 size);

void orion5x_setup_pcie_wa_win(u32 base, u32 size);

void orion5x_setup_eth_wins(void);



/*

 * Shared code used internally by other Orion core functions.

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