drm/amd/display: Add DCN3 DMUB (5baebf61) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -88,6 +88,9 @@ enum dmub_asic {
		DMUB_ASIC_NONE = 0,
		DMUB_ASIC_DCN20,
		DMUB_ASIC_DCN21,
		#ifdef CONFIG_DRM_AMD_DC_DCN3_0
		DMUB_ASIC_DCN30,
		#endif
		DMUB_ASIC_MAX,
		};

drivers/gpu/drm/amd/display/dmub/src/Makefile

+3 −0

Original line number	Diff line number	Diff line
		@@ -21,6 +21,9 @@
		#

		DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
		ifdef CONFIG_DRM_AMD_DC_DCN3_0
		DMUB += dmub_dcn30.o
		endif

		AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

0 → 100644

+184 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2020 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#include "../dmub_srv.h"
		#include "dmub_reg.h"
		#include "dmub_dcn20.h"

		#include "sienna_cichlid_ip_offset.h"
		#include "dcn/dcn_3_0_0_offset.h"
		#include "dcn/dcn_3_0_0_sh_mask.h"

		#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
		#define CTX dmub
		#define REGS dmub->regs

		/* Registers. */

		const struct dmub_srv_common_regs dmub_srv_dcn30_regs = {
		#define DMUB_SR(reg) REG_OFFSET(reg),
		{ DMUB_COMMON_REGS() },
		#undef DMUB_SR

		#define DMUB_SF(reg, field) FD_MASK(reg, field),
		{ DMUB_COMMON_FIELDS() },
		#undef DMUB_SF

		#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
		{ DMUB_COMMON_FIELDS() },
		#undef DMUB_SF
		};

		/* Shared functions. */

		static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,
		uint64_t *fb_base,
		uint64_t *fb_offset)
		{
		uint32_t tmp;

		if (dmub->fb_base \|\| dmub->fb_offset) {
		*fb_base = dmub->fb_base;
		*fb_offset = dmub->fb_offset;
		return;
		}

		REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
		*fb_base = (uint64_t)tmp << 24;

		REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
		*fb_offset = (uint64_t)tmp << 24;
		}

		static inline void dmub_dcn30_translate_addr(const union dmub_addr *addr_in,
		uint64_t fb_base,
		uint64_t fb_offset,
		union dmub_addr *addr_out)
		{
		addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
		}

		void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,
		const struct dmub_window *cw0,
		const struct dmub_window *cw1)
		{
		union dmub_addr offset;
		uint64_t fb_base, fb_offset;

		dmub_dcn30_get_fb_base_offset(dmub, &fb_base, &fb_offset);

		REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

		/* MEM_CTNL read/write space doesn't exist. */

		dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);

		REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
		REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
		REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
		DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
		DMCUB_REGION3_CW0_ENABLE, 1);

		dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);

		REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
		REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
		REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
		DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
		DMCUB_REGION3_CW1_ENABLE, 1);

		REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
		0x20);
		}

		void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
		const struct dmub_window *cw2,
		const struct dmub_window *cw3,
		const struct dmub_window *cw4,
		const struct dmub_window *cw5,
		const struct dmub_window *cw6)
		{
		union dmub_addr offset;

		/* sienna_cichlid has hardwired virtual addressing for CW2-CW7 */

		offset = cw2->offset;

		if (cw2->region.base != cw2->region.top) {
		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
		REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
		DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
		DMCUB_REGION3_CW2_ENABLE, 1);
		} else {
		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
		REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
		}

		offset = cw3->offset;

		REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
		REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
		REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
		DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
		DMCUB_REGION3_CW3_ENABLE, 1);

		offset = cw4->offset;

		REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
		REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
		cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
		1);

		offset = cw5->offset;

		REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
		REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
		REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
		DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
		DMCUB_REGION3_CW5_ENABLE, 1);

		offset = cw6->offset;

		REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
		REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
		REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
		REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
		DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
		DMCUB_REGION3_CW6_ENABLE, 1);
		}

		bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub)
		{
		return (REG_READ(DMCUB_SCRATCH0) > 0);
		}

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h

0 → 100644

+50 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2020 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#ifndef _DMUB_DCN30_H_
		#define _DMUB_DCN30_H_

		#include "dmub_dcn20.h"

		/* Registers. */

		extern const struct dmub_srv_common_regs dmub_srv_dcn30_regs;

		/* Hardware functions. */

		void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,
		const struct dmub_window *cw0,
		const struct dmub_window *cw1);

		void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
		const struct dmub_window *cw2,
		const struct dmub_window *cw3,
		const struct dmub_window *cw4,
		const struct dmub_window *cw5,
		const struct dmub_window *cw6);

		bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub);

		#endif /* _DMUB_DCN30_H_ */

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

+15 −0

Original line number	Diff line number	Diff line
		@@ -27,6 +27,9 @@
		#include "dmub_dcn20.h"
		#include "dmub_dcn21.h"
		#include "dmub_cmd.h"
		#ifdef CONFIG_DRM_AMD_DC_DCN3_0
		#include "dmub_dcn30.h"
		#endif
		#include "os_types.h"
		/*
		* Note: the DMUB service is standalone. No additional headers should be
		@@ -133,6 +136,9 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
		switch (asic) {
		case DMUB_ASIC_DCN20:
		case DMUB_ASIC_DCN21:
		#ifdef CONFIG_DRM_AMD_DC_DCN3_0
		case DMUB_ASIC_DCN30:
		#endif
		dmub->regs = &dmub_srv_dcn20_regs;

		funcs->reset = dmub_dcn20_reset;
		@@ -154,6 +160,15 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
		funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
		funcs->is_phy_init = dmub_dcn21_is_phy_init;
		}
		#ifdef CONFIG_DRM_AMD_DC_DCN3_0
		if (asic == DMUB_ASIC_DCN30) {
		dmub->regs = &dmub_srv_dcn30_regs;

		funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done;
		funcs->backdoor_load = dmub_dcn30_backdoor_load;
		funcs->setup_windows = dmub_dcn30_setup_windows;
		}
		#endif
		break;

		default:

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