Commit 5bab858e authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add rlc iram and dram firmware support 



Support to load RLC iram and dram ucode when RLC firmware struct use v2.2

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5fe19ce8

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+6 −0
Original line number Diff line number Diff line
@@ -1752,6 +1752,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 
	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:

		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;

		break;

	case AMDGPU_UCODE_ID_RLC_IRAM:

		*type = GFX_FW_TYPE_RLC_IRAM;

		break;

	case AMDGPU_UCODE_ID_RLC_DRAM:

		*type = GFX_FW_TYPE_RLC_DRAM_BOOT;

		break;

	case AMDGPU_UCODE_ID_SMC:

		*type = GFX_FW_TYPE_SMU;

		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

+4 −0
Original line number Diff line number Diff line
@@ -168,12 +168,16 @@ struct amdgpu_rlc { 
	u32 save_restore_list_cntl_size_bytes;

	u32 save_restore_list_gpm_size_bytes;

	u32 save_restore_list_srm_size_bytes;

	u32 rlc_iram_ucode_size_bytes;

	u32 rlc_dram_ucode_size_bytes;



	u32 *register_list_format;

	u32 *register_restore;

	u8 *save_restore_list_cntl;

	u8 *save_restore_list_gpm;

	u8 *save_restore_list_srm;

	u8 *rlc_iram_ucode;

	u8 *rlc_dram_ucode;



	bool is_rlc_v2_1;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

+10 −0
Original line number Diff line number Diff line
@@ -502,6 +502,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
@@ -558,6 +560,14 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {

		ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {

		ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {

		ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);

		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+11 −0
Original line number Diff line number Diff line
@@ -222,6 +222,15 @@ struct rlc_firmware_header_v2_1 { 
	uint32_t save_restore_list_srm_offset_bytes;

};



/* version_major=2, version_minor=1 */

struct rlc_firmware_header_v2_2 {

	struct rlc_firmware_header_v2_1 v2_1;

	uint32_t rlc_iram_ucode_size_bytes;

	uint32_t rlc_iram_ucode_offset_bytes;

	uint32_t rlc_dram_ucode_size_bytes;

	uint32_t rlc_dram_ucode_offset_bytes;

};



/* version_major=1, version_minor=0 */

struct sdma_firmware_header_v1_0 {

	struct common_firmware_header header;
@@ -339,6 +348,8 @@ enum AMDGPU_UCODE_ID { 
	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,

	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,

	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,

	AMDGPU_UCODE_ID_RLC_IRAM,

	AMDGPU_UCODE_ID_RLC_DRAM,

	AMDGPU_UCODE_ID_RLC_G,

	AMDGPU_UCODE_ID_STORAGE,

	AMDGPU_UCODE_ID_SMC,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+33 −6
Original line number Diff line number Diff line
@@ -3717,6 +3717,17 @@ static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 
			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);

}



static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_2 *rlc_hdr;



	rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);

	adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);

	adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);

	adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);

}



static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)

{

	bool ret = false;
@@ -3838,8 +3849,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;

		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);

		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);

		if (version_major == 2 && version_minor == 1)

			adev->gfx.rlc.is_rlc_v2_1 = true;



		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);

		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
@@ -3881,8 +3890,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)

			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);



		if (adev->gfx.rlc.is_rlc_v2_1)

		if (version_major == 2) {

			if (version_minor >= 1)

				gfx_v10_0_init_rlc_ext_microcode(adev);

			if (version_minor == 2)

				gfx_v10_0_init_rlc_iram_dram_microcode(adev);

		}

	}



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
@@ -3943,8 +3956,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
			adev->firmware.fw_size +=

				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

		}

		if (adev->gfx.rlc.is_rlc_v2_1 &&

		    adev->gfx.rlc.save_restore_list_cntl_size_bytes &&

		if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&

		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&

		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
@@ -3964,6 +3976,21 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);



			if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&

			    adev->gfx.rlc.rlc_dram_ucode_size_bytes) {

				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];

				info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;

				info->fw = adev->gfx.rlc_fw;

				adev->firmware.fw_size +=

					ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);



				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];

				info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;

				info->fw = adev->gfx.rlc_fw;

				adev->firmware.fw_size +=

					ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);

			}

		}



		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];

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