Commit 5ba76675 authored by Graf Yang's avatar Graf Yang Committed by Mike Frysinger
Browse files

Blackfin: work around anomaly 05000220 



When possible, work around anomaly 05000220 (external memory is write
back cached, but L2 is not cached).  If not possible, detect the
conditions at build time and reject any qualifying configurations.

Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent a261eec0

arch/blackfin/Kconfig

+17 −7
Original line number Diff line number Diff line
@@ -913,7 +913,7 @@ config BFIN_ICACHE_LOCK 
	bool "Enable Instruction Cache Locking"



choice

	prompt "Policy"

	prompt "External memory cache policy"

	depends on BFIN_DCACHE

	default BFIN_WB if !SMP

	default BFIN_WT if SMP
@@ -954,12 +954,22 @@ config BFIN_WT 


endchoice



config BFIN_L2_CACHEABLE

	bool "Cache L2 SRAM"

	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))

	default n

	help

	  Select to make L2 SRAM cacheable in L1 data and instruction cache.

choice

	prompt "L2 SRAM cache policy"

	depends on (BF54x || BF561)

	default BFIN_L2_WT

config BFIN_L2_WB

	bool "Write back"

	depends on !SMP



config BFIN_L2_WT

	bool "Write through"

	depends on !SMP



config BFIN_L2_NOT_CACHED

	bool "Not cached"



endchoice



config MPU

	bool "Enable the memory protection unit (EXPERIMENTAL)"

arch/blackfin/include/asm/cplb.h

+19 −16
Original line number Diff line number Diff line
@@ -53,29 +53,32 @@ 
#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)

#endif



#define SDRAM_DNON_CHBL  (CPLB_COMMON)

#define SDRAM_EBIU       (CPLB_COMMON)

#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)



#define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)



#ifdef CONFIG_SMP

#define L2_ATTR          (INITIAL_T | I_CPLB | D_CPLB)

#define L2_IMEMORY         (CPLB_COMMON | CPLB_LOCK)

#define L2_DMEMORY         (CPLB_COMMON | CPLB_LOCK)

#define L2_IMEMORY       (CPLB_COMMON)

#define L2_DMEMORY       (CPLB_LOCK | CPLB_COMMON)



#else

#ifdef CONFIG_BFIN_L2_CACHEABLE

#define L2_ATTR          (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)

#define L2_IMEMORY       (SDRAM_IGENERIC)

#define L2_DMEMORY        (SDRAM_DGENERIC)

#else

#define L2_IMEMORY        (CPLB_COMMON)

#define L2_DMEMORY        (CPLB_COMMON)

#endif /* CONFIG_BFIN_L2_CACHEABLE */



#define L2_ATTR           (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)

# if defined(CONFIG_BFIN_L2_WB)

# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_COMMON)

# elif defined(CONFIG_BFIN_L2_WT)

# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)

# elif defined(CONFIG_BFIN_L2_NOT_CACHED)

# define L2_DMEMORY      (CPLB_COMMON)

# else

# define L2_DMEMORY      (0)

# endif

#endif /* CONFIG_SMP */



#define SDRAM_DNON_CHBL  (CPLB_COMMON)

#define SDRAM_EBIU       (CPLB_COMMON)

#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)



#define SIZE_1K 0x00000400      /* 1K */

#define SIZE_4K 0x00001000      /* 4K */

#define SIZE_1M 0x00100000      /* 1M */

arch/blackfin/mach-common/arch_checks.c

+7 −0
Original line number Diff line number Diff line
@@ -71,3 +71,10 @@ 
#if ANOMALY_05000448

# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.

#endif



/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */

#if ANOMALY_05000220 && \

	((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \

	 (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB)))

# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.

#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE