Commit 5b8ea6bf authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.3-rockchip-dts32-1' of... 

Merge tag 'v5.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

A lot more love for rk3288 in general and veyron specially with changes
all over the place.

* tag 'v5.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

: (21 commits)
  ARM: dts: rockchip: Split GPIO keys for veyron into multiple devices
  ARM: dts: rockchip: Add HDMI i2c unwedging for rk3288-veyron
  ARM: dts: rockchip: Add unwedge pinctrl entries for dw_hdmi on rk3288
  ARM: dts: rockchip: Switch to builtin HDMI DDC bus on rk3288-veyron
  ARM: dts: rockchip: Add pin names for rk3288-veyron jaq, mickey, speedy
  ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3
  ARM: dts: rockchip: Configure the GPU thermal zone for mickey
  ARM: dts: rockchip: Use the GPU to cool CPU thermal zone of veyron mickey
  ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288
  ARM: dts: rockchip: Use GPU as cooling device for the GPU thermal zone of the rk3288
  ARM: dts: rockchip: Add #cooling-cells entry for rk3288 GPU
  ARM: dts: rockchip: Mark that the rk3288 timer might stop in suspend
  ARM: dts: rockchip: Add pin names for rk3288-veyron-jerry
  ARM: dts: rockchip: Add pin names for rk3288-veyron-minnie
  ARM: dts: raise GPU trip point temperature for speedy to 80 degC
  ARM: dts: rockchip: raise GPU trip point temperatures for veyron
  ARM: dts: rockchip: raise CPU trip point temperature for veyron to 100 degC
  ARM: dts: rockchip: Make rk3288-veyron-minnie run at hs200
  ARM: dts: rockchip: Make rk3288-veyron-mickey's emmc work again
  ARM: dts: rockchip: Remove bogus 'i2s_clk_out' from rk3288-veyron-mickey
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0763d0c2 b8925b7c

arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi

+15 −12
Original line number Diff line number Diff line
@@ -70,6 +70,21 @@ 
		pinctrl-0 = <&ac_present_ap>;

	};



	lid_switch: lid-switch {

		compatible = "gpio-keys";

		pinctrl-names = "default";

		pinctrl-0 = <&ap_lid_int_l>;



		lid {

			label = "Lid";

			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;

			wakeup-source;

			linux,code = <SW_LID>;

			linux,input-type = <EV_SW>;

			debounce-interval = <1>;

		};

	};



	panel: panel {

		compatible ="innolux,n116bge", "simple-panel";

		status = "okay";
@@ -149,18 +164,6 @@ 
	status = "okay";

};



&gpio_keys {

	pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;

	lid {

		label = "Lid";

		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;

		wakeup-source;

		linux,code = <0>; /* SW_LID */

		linux,input-type = <5>; /* EV_SW */

		debounce-interval = <1>;

	};

};



&pwm0 {

	status = "okay";

};

arch/arm/boot/dts/rk3288-veyron-jaq.dts

+207 −0
Original line number Diff line number Diff line
@@ -135,6 +135,213 @@ 
	pinctrl-0 = <&vcc50_hdmi_en>;

};



&gpio0 {

	gpio-line-names = "PMIC_SLEEP_AP",

			  "DDRIO_PWROFF",

			  "DDRIO_RETEN",

			  "TS3A227E_INT_L",

			  "PMIC_INT_L",

			  "PWR_KEY_L",

			  "AP_LID_INT_L",

			  "EC_IN_RW",



			  "AC_PRESENT_AP",

			  /*

			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call

			   * it REC_MODE_L.

			   */

			  "RECOVERY_SW_L",

			  "OTP_OUT",

			  "HOST1_PWR_EN",

			  "USBOTG_PWREN_H",

			  "AP_WARM_RESET_H",

			  "nFALUT2",

			  "I2C0_SDA_PMIC",



			  "I2C0_SCL_PMIC",

			  "SUSPEND_L",

			  "USB_INT";

};



&gpio2 {

	gpio-line-names = "CONFIG0",

			  "CONFIG1",

			  "CONFIG2",

			  "",

			  "",

			  "",

			  "",

			  "CONFIG3",



			  "",

			  "EMMC_RST_L",

			  "",

			  "",

			  "BL_PWR_EN",

			  "AVDD_1V8_DISP_EN";

};



&gpio3 {

	gpio-line-names = "FLASH0_D0",

			  "FLASH0_D1",

			  "FLASH0_D2",

			  "FLASH0_D3",

			  "FLASH0_D4",

			  "FLASH0_D5",

			  "FLASH0_D6",

			  "FLASH0_D7",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "FLASH0_CS2/EMMC_CMD",

			  "",

			  "FLASH0_DQS/EMMC_CLKO";

};



&gpio4 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "UART0_RXD",

			  "UART0_TXD",

			  "UART0_CTS",

			  "UART0_RTS",

			  "SDIO0_D0",

			  "SDIO0_D1",

			  "SDIO0_D2",

			  "SDIO0_D3",



			  "SDIO0_CMD",

			  "SDIO0_CLK",

			  "BT_DEV_WAKE",	/* Maybe missing from mighty? */

			  "",

			  "WIFI_ENABLE_H",

			  "BT_ENABLE_L",

			  "WIFI_HOST_WAKE",

			  "BT_HOST_WAKE";

};



&gpio5 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "",

			  "",

			  "SPI0_CLK",

			  "SPI0_CS0",

			  "SPI0_TXD",

			  "SPI0_RXD",



			  "",

			  "",

			  "",

			  "VCC50_HDMI_EN";

};



&gpio6 {

	gpio-line-names = "I2S0_SCLK",

			  "I2S0_LRCK_RX",

			  "I2S0_LRCK_TX",

			  "I2S0_SDI",

			  "I2S0_SDO0",

			  "HP_DET_H",

			  "ALS_INT",

			  "INT_CODEC",



			  "I2S0_CLK",

			  "I2C2_SDA",

			  "I2C2_SCL",

			  "MICDET",

			  "",

			  "",

			  "",

			  "",



			  "SDMMC_D0",

			  "SDMMC_D1",

			  "SDMMC_D2",

			  "SDMMC_D3",

			  "SDMMC_CLK",

			  "SDMMC_CMD";

};



&gpio7 {

	gpio-line-names = "LCDC_BL",

			  "PWM_LOG",

			  "BL_EN",

			  "TRACKPAD_INT",

			  "TPM_INT_H",

			  "SDMMC_DET_L",

			  /*

			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call

			   * it FW_WP_AP.

			   */

			  "AP_FLASH_WP_L",

			  "EC_INT",



			  "CPU_NMI",

			  "DVSOK",

			  "SDMMC_WP",		/* mighty only */

			  "EDP_HPD",

			  "DVS1",

			  "nFALUT1",		/* nFAULT1 on jaq */

			  "LCD_EN",

			  "DVS2",



			  "VCC5V_GOOD_H",

			  "I2C4_SDA_TP",

			  "I2C4_SCL_TP",

			  "I2C5_SDA_HDMI",

			  "I2C5_SCL_HDMI",

			  "5V_DRV",

			  "UART2_RXD",

			  "UART2_TXD";

};



&gpio8 {

	gpio-line-names = "RAM_ID0",

			  "RAM_ID1",

			  "RAM_ID2",

			  "RAM_ID3",

			  "I2C1_SDA_TPM",

			  "I2C1_SCL_TPM",

			  "SPI2_CLK",

			  "SPI2_CS0",



			  "SPI2_RXD",

			  "SPI2_TXD";

};



&pinctrl {

	backlight {

		bl_pwr_en: bl_pwr_en {

arch/arm/boot/dts/rk3288-veyron-jerry.dts

+207 −0
Original line number Diff line number Diff line
@@ -103,6 +103,213 @@ 
	pinctrl-0 = <&vcc50_hdmi_en>;

};



&gpio0 {

	gpio-line-names = "PMIC_SLEEP_AP",

			  "DDRIO_PWROFF",

			  "DDRIO_RETEN",

			  "TS3A227E_INT_L",

			  "PMIC_INT_L",

			  "PWR_KEY_L",

			  "AP_LID_INT_L",

			  "EC_IN_RW",



			  "AC_PRESENT_AP",

			  /*

			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call

			   * it REC_MODE_L.

			   */

			  "RECOVERY_SW_L",

			  "OTP_OUT",

			  "HOST1_PWR_EN",

			  "USBOTG_PWREN_H",

			  "AP_WARM_RESET_H",

			  "nFAULT2",

			  "I2C0_SDA_PMIC",



			  "I2C0_SCL_PMIC",

			  "SUSPEND_L",

			  "USB_INT";

};



&gpio2 {

	gpio-line-names = "CONFIG0",

			  "CONFIG1",

			  "CONFIG2",

			  "",

			  "",

			  "",

			  "",

			  "CONFIG3",



			  "",

			  "EMMC_RST_L",

			  "",

			  "",

			  "BL_PWR_EN",

			  "AVDD_1V8_DISP_EN";

};



&gpio3 {

	gpio-line-names = "FLASH0_D0",

			  "FLASH0_D1",

			  "FLASH0_D2",

			  "FLASH0_D3",

			  "FLASH0_D4",

			  "FLASH0_D5",

			  "FLASH0_D6",

			  "FLASH0_D7",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "FLASH0_CS2/EMMC_CMD",

			  "",

			  "FLASH0_DQS/EMMC_CLKO";

};



&gpio4 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "UART0_RXD",

			  "UART0_TXD",

			  "UART0_CTS",

			  "UART0_RTS",

			  "SDIO0_D0",

			  "SDIO0_D1",

			  "SDIO0_D2",

			  "SDIO0_D3",



			  "SDIO0_CMD",

			  "SDIO0_CLK",

			  "BT_DEV_WAKE",

			  "",

			  "WIFI_ENABLE_H",

			  "BT_ENABLE_L",

			  "WIFI_HOST_WAKE",

			  "BT_HOST_WAKE";

};



&gpio5 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "",

			  "",

			  "SPI0_CLK",

			  "SPI0_CS0",

			  "SPI0_TXD",

			  "SPI0_RXD",



			  "",

			  "",

			  "",

			  "VCC50_HDMI_EN";

};



&gpio6 {

	gpio-line-names = "I2S0_SCLK",

			  "I2S0_LRCK_RX",

			  "I2S0_LRCK_TX",

			  "I2S0_SDI",

			  "I2S0_SDO0",

			  "HP_DET_H",

			  "",

			  "INT_CODEC",



			  "I2S0_CLK",

			  "I2C2_SDA",

			  "I2C2_SCL",

			  "MICDET",

			  "",

			  "",

			  "",

			  "",



			  "SDMMC_D0",

			  "SDMMC_D1",

			  "SDMMC_D2",

			  "SDMMC_D3",

			  "SDMMC_CLK",

			  "SDMMC_CMD";

};



&gpio7 {

	gpio-line-names = "LCDC_BL",

			  "PWM_LOG",

			  "BL_EN",

			  "TRACKPAD_INT",

			  "TPM_INT_H",

			  "SDMMC_DET_L",

			  /*

			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call

			   * it FW_WP_AP.

			   */

			  "AP_FLASH_WP_L",

			  "EC_INT",



			  "CPU_NMI",

			  "DVSOK",

			  "",

			  "EDP_HPD",

			  "DVS1",

			  "nFAULT1",

			  "LCD_EN",

			  "DVS2",



			  "VCC5V_GOOD_H",

			  "I2C4_SDA_TP",

			  "I2C4_SCL_TP",

			  "I2C5_SDA_HDMI",

			  "I2C5_SCL_HDMI",

			  "5V_DRV",

			  "UART2_RXD",

			  "UART2_TXD";

};



&gpio8 {

	gpio-line-names = "RAM_ID0",

			  "RAM_ID1",

			  "RAM_ID2",

			  "RAM_ID3",

			  "I2C1_SDA_TPM",

			  "I2C1_SCL_TPM",

			  "SPI2_CLK",

			  "SPI2_CS0",



			  "SPI2_RXD",

			  "SPI2_TXD";

};



&pinctrl {

	backlight {

		bl_pwr_en: bl_pwr_en {

arch/arm/boot/dts/rk3288-veyron-mickey.dts

+227 −7
Original line number Diff line number Diff line
@@ -75,9 +75,7 @@ 
	cooling-maps {

		/*

		 * After 1st level, throttle the CPU down to as low as 1.4 GHz

		 * and don't let the GPU go faster than 400 MHz.  Note that we

		 * won't throttle the GPU lower than 400 MHz due to CPU

		 * heat--we'll let the GPU do the rest itself.

		 * and don't let the GPU go faster than 400 MHz.

		 */

		cpu_warm_limit_cpu {

			trip = <&cpu_alert_warm>;
@@ -86,6 +84,10 @@ 
					 <&cpu2 THERMAL_NO_LIMIT 4>,

					 <&cpu3 THERMAL_NO_LIMIT 4>;

		};

		cpu_warm_limit_gpu {

			trip = <&cpu_alert_warm>;

			cooling-device = <&gpu 1 1>;

		};



		/*

		 * Add some discrete steps to help throttling system deal
@@ -125,11 +127,80 @@ 
					 <&cpu2 8 THERMAL_NO_LIMIT>,

					 <&cpu3 8 THERMAL_NO_LIMIT>;

		};



		/* At very hot, don't let GPU go over 300 MHz */

		cpu_very_hot_limit_gpu {

			trip = <&cpu_alert_very_hot>;

			cooling-device = <&gpu 2 2>;

		};

	};

};



&gpu_thermal {

	/delete-node/ trips;

	/delete-node/ cooling-maps;



	trips {

		gpu_alert_warmish: gpu_alert_warmish {

			temperature = <60000>; /* millicelsius */

			hysteresis = <2000>; /* millicelsius */

			type = "passive";

		};

		gpu_alert_warm: gpu_alert_warm {

			temperature = <65000>; /* millicelsius */

			hysteresis = <2000>; /* millicelsius */

			type = "passive";

		};

		gpu_alert_hotter: gpu_alert_hotter {

			temperature = <84000>; /* millicelsius */

			hysteresis = <2000>; /* millicelsius */

			type = "passive";

		};

		gpu_alert_very_very_hot: gpu_alert_very_very_hot {

			temperature = <86000>; /* millicelsius */

			hysteresis = <2000>; /* millicelsius */

			type = "passive";

		};

		gpu_crit: gpu_crit {

			temperature = <90000>; /* millicelsius */

			hysteresis = <2000>; /* millicelsius */

			type = "critical";

		};

	};



	cooling-maps {

		/* After 1st level throttle the GPU down to as low as 400 MHz */

		gpu_warmish_limit_gpu {

			trip = <&gpu_alert_warmish>;

			cooling-device = <&gpu THERMAL_NO_LIMIT 1>;

		};



&emmc {

	/delete-property/mmc-hs200-1_8v;

		/*

		 * Slightly after we throttle the GPU, we'll also make sure that

		 * the CPU can't go faster than 1.4 GHz.  Note that we won't

		 * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll

		 * let the CPU do the rest itself.

		 */

		gpu_warm_limit_cpu {

			trip = <&gpu_alert_warm>;

			cooling-device = <&cpu0 4 4>,

					 <&cpu1 4 4>,

					 <&cpu2 4 4>,

					 <&cpu3 4 4>;

		};



		/* When hot, GPU goes down to 300 MHz */

		gpu_hotter_limit_gpu {

			trip = <&gpu_alert_hotter>;

			cooling-device = <&gpu 2 2>;

		};



		/* When really hot, don't let GPU go _above_ 300 MHz */

		gpu_very_very_hot_limit_gpu {

			trip = <&gpu_alert_very_very_hot>;

			cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;

		};

	};

};



&i2c2 {
@@ -142,8 +213,6 @@ 


&i2s {

	status = "okay";

	clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";

	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;

};



&rk808 {
@@ -183,6 +252,157 @@ 
	};

};



&gpio0 {

	gpio-line-names = "PMIC_SLEEP_AP",

			  "",

			  "",

			  "",

			  "PMIC_INT_L",

			  "POWER_BUTTON_L",

			  "",

			  "",



			  "",

			  /*

			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call

			   * it REC_MODE_L.

			   */

			  "RECOVERY_SW_L",

			  "OT_RESET",

			  "",

			  "",

			  "AP_WARM_RESET_H",

			  "",

			  "I2C0_SDA_PMIC",



			  "I2C0_SCL_PMIC",

			  "",

			  "nFALUT";

};



&gpio2 {

	gpio-line-names = "CONFIG0",

			  "CONFIG1",

			  "CONFIG2",

			  "",

			  "",

			  "",

			  "",

			  "CONFIG3",



			  "",

			  "EMMC_RST_L";

};



&gpio3 {

	gpio-line-names = "FLASH0_D0",

			  "FLASH0_D1",

			  "FLASH0_D2",

			  "FLASH0_D3",

			  "FLASH0_D4",

			  "FLASH0_D5",

			  "FLASH0_D6",

			  "FLASH0_D7",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "FLASH0_CS2/EMMC_CMD",

			  "",

			  "FLASH0_DQS/EMMC_CLKO";

};



&gpio4 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "UART0_RXD",

			  "UART0_TXD",

			  "UART0_CTS_L",

			  "UART0_RTS_L",

			  "SDIO0_D0",

			  "SDIO0_D1",

			  "SDIO0_D2",

			  "SDIO0_D3",



			  "SDIO0_CMD",

			  "SDIO0_CLK",

			  "BT_DEV_WAKE",

			  "",

			  "WIFI_ENABLE_H",

			  "BT_ENABLE_L",

			  "WIFI_HOST_WAKE",

			  "BT_HOST_WAKE";

};



&gpio7 {

	gpio-line-names = "",

			  "PWM_LOG",

			  "",

			  "",

			  "TPM_INT_H",

			  "SDMMC_DET_L",

			  /*

			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call

			   * it FW_WP_AP.

			   */

			  "AP_FLASH_WP_L",

			  "",



			  "CPU_NMI",

			  "DVSOK",

			  "HDMI_WAKE",

			  "POWER_HDMI_ON",

			  "DVS1",

			  "",

			  "",

			  "DVS2",



			  "HDMI_CEC",

			  "",

			  "",

			  "I2C5_SDA_HDMI",

			  "I2C5_SCL_HDMI",

			  "",

			  "UART2_RXD",

			  "UART2_TXD";

};



&gpio8 {

	gpio-line-names = "RAM_ID0",

			  "RAM_ID1",

			  "RAM_ID2",

			  "RAM_ID3",

			  "I2C1_SDA_TPM",

			  "I2C1_SCL_TPM",

			  "SPI2_CLK",

			  "SPI2_CS0",



			  "SPI2_RXD",

			  "SPI2_TXD";

};



&pinctrl {

	hdmi {

		power_hdmi_on: power-hdmi-on {

arch/arm/boot/dts/rk3288-veyron-minnie.dts

+232 −22
Original line number Diff line number Diff line
@@ -48,6 +48,26 @@ 
		regulator-boot-on;

		vin-supply = <&vcc18_wl>;

	};



	volume_buttons: volume-buttons {

		compatible = "gpio-keys";

		pinctrl-names = "default";

		pinctrl-0 = <&volum_down_l &volum_up_l>;



		volum_down {

			label = "Volum_down";

			gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;

			linux,code = <KEY_VOLUMEDOWN>;

			debounce-interval = <100>;

		};



		volum_up {

			label = "Volum_up";

			gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;

			linux,code = <KEY_VOLUMEUP>;

			debounce-interval = <100>;

		};

	};

};



&backlight {
@@ -90,28 +110,6 @@ 
	pwm-off-delay-ms = <200>;

};



&emmc {

	/delete-property/mmc-hs200-1_8v;

};



&gpio_keys {

	pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>;



	volum_down {

		label = "Volum_down";

		gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;

		linux,code = <KEY_VOLUMEDOWN>;

		debounce-interval = <100>;

	};



	volum_up {

		label = "Volum_up";

		gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;

		linux,code = <KEY_VOLUMEUP>;

		debounce-interval = <100>;

	};

};



&i2c_tunnel {

	battery: bq27500@55 {

		compatible = "ti,bq27500";
@@ -188,6 +186,218 @@ 
	pinctrl-0 = <&vcc50_hdmi_en>;

};



&gpio0 {

	gpio-line-names = "PMIC_SLEEP_AP",

			  "DDRIO_PWROFF",

			  "DDRIO_RETEN",

			  "TS3A227E_INT_L",

			  "PMIC_INT_L",

			  "PWR_KEY_L",

			  "AP_LID_INT_L",

			  "EC_IN_RW",



			  "AC_PRESENT_AP",

			  /*

			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call

			   * it REC_MODE_L.

			   */

			  "RECOVERY_SW_L",

			  "OTP_OUT",

			  "HOST1_PWR_EN",

			  "USBOTG_PWREN_H",

			  "AP_WARM_RESET_H",

			  "nFALUT2",

			  "I2C0_SDA_PMIC",



			  "I2C0_SCL_PMIC",

			  "SUSPEND_L",

			  "USB_INT";

};



&gpio2 {

	gpio-line-names = "CONFIG0",

			  "CONFIG1",

			  "CONFIG2",

			  "",

			  "",

			  "",

			  "",

			  "CONFIG3",



			  "PROCHOT#",

			  "EMMC_RST_L",

			  "",

			  "",

			  "BL_PWR_EN",

			  "AVDD_1V8_DISP_EN",

			  "TOUCH_INT",

			  "TOUCH_RST",



			  "I2C3_SCL_TP",

			  "I2C3_SDA_TP";

};



&gpio3 {

	gpio-line-names = "FLASH0_D0",

			  "FLASH0_D1",

			  "FLASH0_D2",

			  "FLASH0_D3",

			  "FLASH0_D4",

			  "FLASH0_D5",

			  "FLASH0_D6",

			  "FLASH0_D7",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "FLASH0_CS2/EMMC_CMD",

			  "",

			  "FLASH0_DQS/EMMC_CLKO";

};



&gpio4 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "UART0_RXD",

			  "UART0_TXD",

			  "UART0_CTS",

			  "UART0_RTS",

			  "SDIO0_D0",

			  "SDIO0_D1",

			  "SDIO0_D2",

			  "SDIO0_D3",



			  "SDIO0_CMD",

			  "SDIO0_CLK",

			  "dev_wake",

			  "",

			  "WIFI_ENABLE_H",

			  "BT_ENABLE_L",

			  "WIFI_HOST_WAKE",

			  "BT_HOST_WAKE";

};



&gpio5 {

	gpio-line-names = "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",

			  "",

			  "Volum_Up#",

			  "Volum_Down#",

			  "SPI0_CLK",

			  "SPI0_CS0",

			  "SPI0_TXD",

			  "SPI0_RXD",



			  "",

			  "",

			  "",

			  "VCC50_HDMI_EN";

};



&gpio6 {

	gpio-line-names = "I2S0_SCLK",

			  "I2S0_LRCK_RX",

			  "I2S0_LRCK_TX",

			  "I2S0_SDI",

			  "I2S0_SDO0",

			  "HP_DET_H",

			  "",

			  "INT_CODEC",



			  "I2S0_CLK",

			  "I2C2_SDA",

			  "I2C2_SCL",

			  "MICDET",

			  "",

			  "",

			  "",

			  "",



			  "SDMMC_D0",

			  "SDMMC_D1",

			  "SDMMC_D2",

			  "SDMMC_D3",

			  "SDMMC_CLK",

			  "SDMMC_CMD";

};



&gpio7 {

	gpio-line-names = "LCDC_BL",

			  "PWM_LOG",

			  "BL_EN",

			  "TRACKPAD_INT",

			  "TPM_INT_H",

			  "SDMMC_DET_L",

			  /*

			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call

			   * it FW_WP_AP.

			   */

			  "AP_FLASH_WP_L",

			  "EC_INT",



			  "CPU_NMI",

			  "DVS_OK",

			  "SDMMC_WP",

			  "EDP_HPD",

			  "DVS1",

			  "nFALUT1",

			  "LCD_EN",

			  "DVS2",



			  "VCC5V_GOOD_H",

			  "I2C4_SDA_TP",

			  "I2C4_SCL_TP",

			  "I2C5_SDA_HDMI",

			  "I2C5_SCL_HDMI",

			  "5V_DRV",

			  "UART2_RXD",

			  "UART2_TXD";

};



&gpio8 {

	gpio-line-names = "RAM_ID0",

			  "RAM_ID1",

			  "RAM_ID2",

			  "RAM_ID3",

			  "I2C1_SDA_TPM",

			  "I2C1_SCL_TPM",

			  "SPI2_CLK",

			  "SPI2_CS0",



			  "SPI2_RXD",

			  "SPI2_TXD";

};



&pinctrl {

	backlight {

		bl_pwr_en: bl_pwr_en {

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