Commit 5b735940 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2016-06-06' of git://anongit.freedesktop.org/drm-intel into drm-next 

- some polish for the guc code (Dave Gordon)
- big refactoring of gen9 display clock handling code (Ville)
- refactoring work in the context code (Chris Wilson)
- give encoder/crtc/planes useful names for debug output (Ville)
- improvements to skl/kbl wm computation code (Mahesh Kumar)
- bunch of smaller improvements all over as usual

* tag 'drm-intel-next-2016-06-06' of git://anongit.freedesktop.org/drm-intel: (64 commits)
  drm/i915: Update DRIVER_DATE to 20160606
  drm/i915: Extract physical display dimensions from VBT
  drm/i915: Silence "unexpected child device config size" for VBT on 845g
  drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)
  drm/i915/skl+: calculate plane pixel rate (v4)
  drm/i915/skl+: calculate ddb minimum allocation (v6)
  drm/i915: Don't try to calculate relative data rates during hw readout
  drm/i915: Only ignore eDP ports that are connected
  drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled
  drm/i915: kill STANDARD/CURSOR plane screams
  drm/i915: Give encoders useful names
  drm/i915: Give meaningful names to all the planes
  drm/i915: Don't leak primary/cursor planes on crtc init failure
  drm/i915: Set crtc->name to "pipe A", "pipe B", etc.
  drm/i915: Use plane->name in debug prints
  drm/i915: Use crtc->name in debug messages
  drm/i915: Reject modeset if the dotclock is too high
  drm/i915: Fix NULL pointer deference when out of PLLs in IVB
  drm/i915/ilk: Don't disable SSC source if it's in use
  drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume
  ...
parents 2cca4557 1750d59d

drivers/gpu/drm/i915/i915_debugfs.c

+70 −36
Original line number Diff line number Diff line
@@ -199,13 +199,6 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);

}



static void describe_ctx(struct seq_file *m, struct intel_context *ctx)

{

	seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');

	seq_putc(m, ctx->remap_slice ? 'R' : 'r');

	seq_putc(m, ' ');

}



static int i915_gem_object_list_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;
@@ -424,6 +417,42 @@ static void print_batch_pool_stats(struct seq_file *m, 
	print_file_stats(m, "[k]batch pool", stats);

}



static int per_file_ctx_stats(int id, void *ptr, void *data)

{

	struct i915_gem_context *ctx = ptr;

	int n;



	for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {

		if (ctx->engine[n].state)

			per_file_stats(0, ctx->engine[n].state, data);

		if (ctx->engine[n].ringbuf)

			per_file_stats(0, ctx->engine[n].ringbuf->obj, data);

	}



	return 0;

}



static void print_context_stats(struct seq_file *m,

				struct drm_i915_private *dev_priv)

{

	struct file_stats stats;

	struct drm_file *file;



	memset(&stats, 0, sizeof(stats));



	mutex_lock(&dev_priv->dev->struct_mutex);

	if (dev_priv->kernel_context)

		per_file_ctx_stats(0, dev_priv->kernel_context, &stats);



	list_for_each_entry(file, &dev_priv->dev->filelist, lhead) {

		struct drm_i915_file_private *fpriv = file->driver_priv;

		idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);

	}

	mutex_unlock(&dev_priv->dev->struct_mutex);



	print_file_stats(m, "[k]contexts", stats);

}



#define count_vmas(list, member) do { \

	list_for_each_entry(vma, list, member) { \

		size += i915_gem_obj_total_ggtt_size(vma->obj); \
@@ -528,10 +557,10 @@ static int i915_gem_object_info(struct seq_file *m, void* data) 


	seq_putc(m, '\n');

	print_batch_pool_stats(m, dev_priv);



	mutex_unlock(&dev->struct_mutex);



	mutex_lock(&dev->filelist_mutex);

	print_context_stats(m, dev_priv);

	list_for_each_entry_reverse(file, &dev->filelist, lhead) {

		struct file_stats stats;

		struct task_struct *task;
@@ -1279,6 +1308,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		}

		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",

			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);

		seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);

		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);

		seq_printf(m, "Render p-state ratio: %d\n",

			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
@@ -1989,8 +2019,7 @@ static int i915_context_status(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *engine;

	struct intel_context *ctx;

	enum intel_engine_id id;

	struct i915_gem_context *ctx;

	int ret;



	ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -1998,33 +2027,37 @@ static int i915_context_status(struct seq_file *m, void *unused) 
		return ret;



	list_for_each_entry(ctx, &dev_priv->context_list, link) {

		if (!i915.enable_execlists &&

		    ctx->legacy_hw_ctx.rcs_state == NULL)

			continue;



		seq_printf(m, "HW context %u ", ctx->hw_id);

		describe_ctx(m, ctx);

		if (ctx == dev_priv->kernel_context)

			seq_printf(m, "(kernel context) ");

		if (IS_ERR(ctx->file_priv)) {

			seq_puts(m, "(deleted) ");

		} else if (ctx->file_priv) {

			struct pid *pid = ctx->file_priv->file->pid;

			struct task_struct *task;



		if (i915.enable_execlists) {

			task = get_pid_task(pid, PIDTYPE_PID);

			if (task) {

				seq_printf(m, "(%s [%d]) ",

					   task->comm, task->pid);

				put_task_struct(task);

			}

		} else {

			seq_puts(m, "(kernel) ");

		}



		seq_putc(m, ctx->remap_slice ? 'R' : 'r');

		seq_putc(m, '\n');

			for_each_engine_id(engine, dev_priv, id) {

				struct drm_i915_gem_object *ctx_obj =

					ctx->engine[id].state;

				struct intel_ringbuffer *ringbuf =

					ctx->engine[id].ringbuf;



		for_each_engine(engine, dev_priv) {

			struct intel_context *ce = &ctx->engine[engine->id];



			seq_printf(m, "%s: ", engine->name);

				if (ctx_obj)

					describe_obj(m, ctx_obj);

				if (ringbuf)

					describe_ctx_ringbuf(m, ringbuf);

			seq_putc(m, ce->initialised ? 'I' : 'i');

			if (ce->state)

				describe_obj(m, ce->state);

			if (ce->ringbuf)

				describe_ctx_ringbuf(m, ce->ringbuf);

			seq_putc(m, '\n');

		}

		} else {

			describe_obj(m, ctx->legacy_hw_ctx.rcs_state);

		}



		seq_putc(m, '\n');

	}
@@ -2035,13 +2068,13 @@ static int i915_context_status(struct seq_file *m, void *unused) 
}



static void i915_dump_lrc_obj(struct seq_file *m,

			      struct intel_context *ctx,

			      struct i915_gem_context *ctx,

			      struct intel_engine_cs *engine)

{

	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;

	struct page *page;

	uint32_t *reg_state;

	int j;

	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;

	unsigned long ggtt_offset = 0;



	seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
@@ -2083,7 +2116,7 @@ static int i915_dump_lrc(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *engine;

	struct intel_context *ctx;

	struct i915_gem_context *ctx;

	int ret;



	if (!i915.enable_execlists) {
@@ -2263,7 +2296,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 


static int per_file_ctx(int id, void *ptr, void *data)

{

	struct intel_context *ctx = ptr;

	struct i915_gem_context *ctx = ptr;

	struct seq_file *m = data;

	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
@@ -2504,6 +2537,7 @@ static void i915_guc_client_info(struct seq_file *m, 
	seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",

		client->wq_size, client->wq_offset, client->wq_tail);



	seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);

	seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);

	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);

	seq_printf(m, "\tLast submission result: %d\n", client->retcode);

drivers/gpu/drm/i915/i915_dma.c

+6 −6
Original line number Diff line number Diff line
@@ -507,7 +507,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	 * working irqs for e.g. gmbus and dp aux transfers. */

	intel_modeset_init(dev);



	intel_guc_ucode_init(dev);

	intel_guc_init(dev);



	ret = i915_gem_init(dev);

	if (ret)
@@ -544,7 +544,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 
cleanup_gem:

	i915_gem_fini(dev);

cleanup_irq:

	intel_guc_ucode_fini(dev);

	intel_guc_fini(dev);

	drm_irq_uninstall(dev);

	intel_teardown_gmbus(dev);

cleanup_csr:
@@ -1307,7 +1307,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 


	intel_uncore_sanitize(dev_priv);



	intel_opregion_setup(dev);

	intel_opregion_setup(dev_priv);



	i915_gem_load_init_fences(dev_priv);
@@ -1376,7 +1376,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) 


	if (INTEL_INFO(dev_priv)->num_pipes) {

		/* Must be done after probing outputs */

		intel_opregion_init(dev);

		intel_opregion_register(dev_priv);

		acpi_video_register();

	}
@@ -1395,7 +1395,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) 
	i915_audio_component_cleanup(dev_priv);

	intel_gpu_ips_teardown();

	acpi_video_unregister();

	intel_opregion_fini(dev_priv->dev);

	intel_opregion_unregister(dev_priv);

	i915_teardown_sysfs(dev_priv->dev);

	i915_gem_shrinker_cleanup(dev_priv);

}
@@ -1527,7 +1527,7 @@ int i915_driver_unload(struct drm_device *dev) 
	/* Flush any outstanding unpin_work. */

	flush_workqueue(dev_priv->wq);



	intel_guc_ucode_fini(dev);

	intel_guc_fini(dev);

	i915_gem_fini(dev);

	intel_fbc_cleanup_cfb(dev_priv);

drivers/gpu/drm/i915/i915_drv.c

+9 −9
Original line number Diff line number Diff line
@@ -626,10 +626,10 @@ static int i915_drm_suspend(struct drm_device *dev) 
	i915_save_state(dev);



	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;

	intel_opregion_notify_adapter(dev, opregion_target_state);

	intel_opregion_notify_adapter(dev_priv, opregion_target_state);



	intel_uncore_forcewake_reset(dev_priv, false);

	intel_opregion_fini(dev);

	intel_opregion_unregister(dev_priv);



	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
@@ -747,7 +747,7 @@ static int i915_drm_resume(struct drm_device *dev) 
	mutex_unlock(&dev->struct_mutex);



	i915_restore_state(dev);

	intel_opregion_setup(dev);

	intel_opregion_setup(dev_priv);



	intel_init_pch_refclk(dev);

	drm_mode_config_reset(dev);
@@ -792,7 +792,7 @@ static int i915_drm_resume(struct drm_device *dev) 
	/* Config may have changed between suspend and resume */

	drm_helper_hpd_irq_event(dev);



	intel_opregion_init(dev);

	intel_opregion_register(dev_priv);



	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
@@ -800,7 +800,7 @@ static int i915_drm_resume(struct drm_device *dev) 
	dev_priv->modeset_restore = MODESET_DONE;

	mutex_unlock(&dev_priv->modeset_restore_lock);



	intel_opregion_notify_adapter(dev, PCI_D0);

	intel_opregion_notify_adapter(dev_priv, PCI_D0);



	drm_kms_helper_poll_enable(dev);
@@ -1588,14 +1588,14 @@ static int intel_runtime_suspend(struct device *device) 
	 * FIXME: We really should find a document that references the arguments

	 * used below!

	 */

	if (IS_BROADWELL(dev)) {

	if (IS_BROADWELL(dev_priv)) {

		/*

		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop

		 * being detected, and the call we do at intel_runtime_resume()

		 * won't be able to restore them. Since PCI_D3hot matches the

		 * actual specification and appears to be working, use it.

		 */

		intel_opregion_notify_adapter(dev, PCI_D3hot);

		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);

	} else {

		/*

		 * current versions of firmware which depend on this opregion
@@ -1604,7 +1604,7 @@ static int intel_runtime_suspend(struct device *device) 
		 * to distinguish it from notifications that might be sent via

		 * the suspend path.

		 */

		intel_opregion_notify_adapter(dev, PCI_D1);

		intel_opregion_notify_adapter(dev_priv, PCI_D1);

	}



	assert_forcewakes_inactive(dev_priv);
@@ -1628,7 +1628,7 @@ static int intel_runtime_resume(struct device *device) 
	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));

	disable_rpm_wakeref_asserts(dev_priv);



	intel_opregion_notify_adapter(dev, PCI_D0);

	intel_opregion_notify_adapter(dev_priv, PCI_D0);

	dev_priv->pm.suspended = false;

	if (intel_uncore_unclaimed_mmio(dev_priv))

		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");

drivers/gpu/drm/i915/i915_drv.h

+62 −42
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20160522"

#define DRIVER_DATE		"20160606"



#undef WARN_ON

/* Many gcc seem to no see through this and fall over :( */
@@ -834,9 +834,8 @@ struct i915_ctx_hang_stats { 
/* This must match up with the value previously used for execbuf2.rsvd1. */

#define DEFAULT_CONTEXT_HANDLE 0



#define CONTEXT_NO_ZEROMAP (1<<0)

/**

 * struct intel_context - as the name implies, represents a context.

 * struct i915_gem_context - as the name implies, represents a context.

 * @ref: reference count.

 * @user_handle: userspace tracking identity for this context.

 * @remap_slice: l3 row remapping information.
@@ -854,37 +853,33 @@ struct i915_ctx_hang_stats { 
 * Contexts are memory images used by the hardware to store copies of their

 * internal state.

 */

struct intel_context {

struct i915_gem_context {

	struct kref ref;

	int user_handle;

	uint8_t remap_slice;

	struct drm_i915_private *i915;

	int flags;

	struct drm_i915_file_private *file_priv;

	struct i915_ctx_hang_stats hang_stats;

	struct i915_hw_ppgtt *ppgtt;



	struct i915_ctx_hang_stats hang_stats;



	/* Unique identifier for this context, used by the hw for tracking */

	unsigned long flags;

	unsigned hw_id;

	u32 user_handle;

#define CONTEXT_NO_ZEROMAP		(1<<0)



	/* Legacy ring buffer submission */

	struct {

		struct drm_i915_gem_object *rcs_state;

		bool initialized;

	} legacy_hw_ctx;



	/* Execlists */

	struct {

	struct intel_context {

		struct drm_i915_gem_object *state;

		struct intel_ringbuffer *ringbuf;

		int pin_count;

		struct i915_vma *lrc_vma;

		u64 lrc_desc;

		uint32_t *lrc_reg_state;

		u64 lrc_desc;

		int pin_count;

		bool initialised;

	} engine[I915_NUM_ENGINES];



	struct list_head link;



	u8 remap_slice;

};



enum fb_op_origin {
@@ -1132,6 +1127,8 @@ struct intel_gen6_power_mgmt { 
	bool interrupts_enabled;

	u32 pm_iir;



	u32 pm_intr_keep;



	/* Frequencies are stored in potentially platform dependent multiples.

	 * In other words, *_freq needs to be multiplied by X to be interesting.

	 * Soft limits are those which are used for the dynamic reclocking done
@@ -1715,7 +1712,7 @@ struct i915_execbuffer_params { 
	uint64_t                        batch_obj_vm_offset;

	struct intel_engine_cs *engine;

	struct drm_i915_gem_object      *batch_obj;

	struct intel_context            *ctx;

	struct i915_gem_context            *ctx;

	struct drm_i915_gem_request     *request;

};
@@ -1765,6 +1762,7 @@ struct drm_i915_private { 
	wait_queue_head_t gmbus_wait_queue;



	struct pci_dev *bridge_dev;

	struct i915_gem_context *kernel_context;

	struct intel_engine_cs engine[I915_NUM_ENGINES];

	struct drm_i915_gem_object *semaphore_obj;

	uint32_t last_seqno, next_seqno;
@@ -1820,13 +1818,17 @@ struct drm_i915_private { 
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */



	unsigned int fsb_freq, mem_freq, is_ddr3;

	unsigned int skl_boot_cdclk;

	unsigned int skl_preferred_vco_freq;

	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;

	unsigned int max_dotclk_freq;

	unsigned int rawclk_freq;

	unsigned int hpll_freq;

	unsigned int czclk_freq;



	struct {

		unsigned int vco, ref;

	} cdclk_pll;



	/**

	 * wq - Driver workqueue for GEM.

	 *
@@ -2018,8 +2020,6 @@ struct drm_i915_private { 
		void (*stop_engine)(struct intel_engine_cs *engine);

	} gt;



	struct intel_context *kernel_context;



	/* perform PHY state sanity checks? */

	bool chv_phy_assert[2];
@@ -2386,7 +2386,7 @@ struct drm_i915_gem_request { 
	 * i915_gem_request_free() will then decrement the refcount on the

	 * context.

	 */

	struct intel_context *ctx;

	struct i915_gem_context *ctx;

	struct intel_ringbuffer *ringbuf;



	/**
@@ -2398,7 +2398,7 @@ struct drm_i915_gem_request { 
	 * we keep the previous context pinned until the following (this)

	 * request is retired.

	 */

	struct intel_context *previous_context;

	struct i915_gem_context *previous_context;



	/** Batch buffer related to this request if any (used for

	    error state dump only) */
@@ -2442,7 +2442,7 @@ struct drm_i915_gem_request { 


struct drm_i915_gem_request * __must_check

i915_gem_request_alloc(struct intel_engine_cs *engine,

		       struct intel_context *ctx);

		       struct i915_gem_context *ctx);

void i915_gem_request_free(struct kref *req_ref);

int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,

				   struct drm_file *file);
@@ -2807,8 +2807,14 @@ struct drm_i915_cmd_table { 


#define HAS_CSR(dev)	(IS_GEN9(dev))



#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))

#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))

/*

 * For now, anything with a GuC requires uCode loading, and then supports

 * command submission once loaded. But these are logically independent

 * properties, so we have separate macros to test them.

 */

#define HAS_GUC(dev)		(IS_GEN9(dev) && !IS_KABYLAKE(dev))

#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))

#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))



#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \

				    INTEL_INFO(dev)->gen >= 8)
@@ -3422,22 +3428,36 @@ void i915_gem_context_reset(struct drm_device *dev); 
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);

void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);

int i915_switch_context(struct drm_i915_gem_request *req);

struct intel_context *

i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);

void i915_gem_context_free(struct kref *ctx_ref);

struct drm_i915_gem_object *

i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);

static inline void i915_gem_context_reference(struct intel_context *ctx)



static inline struct i915_gem_context *

i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)

{

	struct i915_gem_context *ctx;



	lockdep_assert_held(&file_priv->dev_priv->dev->struct_mutex);



	ctx = idr_find(&file_priv->context_idr, id);

	if (!ctx)

		return ERR_PTR(-ENOENT);



	return ctx;

}



static inline void i915_gem_context_reference(struct i915_gem_context *ctx)

{

	kref_get(&ctx->ref);

}



static inline void i915_gem_context_unreference(struct intel_context *ctx)

static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)

{

	lockdep_assert_held(&ctx->i915->dev->struct_mutex);

	kref_put(&ctx->ref, i915_gem_context_free);

}



static inline bool i915_gem_context_is_default(const struct intel_context *c)

static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)

{

	return c->user_handle == DEFAULT_CONTEXT_HANDLE;

}
@@ -3607,19 +3627,19 @@ bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, 


/* intel_opregion.c */

#ifdef CONFIG_ACPI

extern int intel_opregion_setup(struct drm_device *dev);

extern void intel_opregion_init(struct drm_device *dev);

extern void intel_opregion_fini(struct drm_device *dev);

extern int intel_opregion_setup(struct drm_i915_private *dev_priv);

extern void intel_opregion_register(struct drm_i915_private *dev_priv);

extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);

extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);

extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,

					 bool enable);

extern int intel_opregion_notify_adapter(struct drm_device *dev,

extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,

					 pci_power_t state);

extern int intel_opregion_get_panel_type(struct drm_device *dev);

extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);

#else

static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }

static inline void intel_opregion_init(struct drm_device *dev) { return; }

static inline void intel_opregion_fini(struct drm_device *dev) { return; }

static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }

static inline void intel_opregion_init(struct drm_i915_private *dev) { }

static inline void intel_opregion_fini(struct drm_i915_private *dev) { }

static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)

{

}
@@ -3629,11 +3649,11 @@ intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 
	return 0;

}

static inline int

intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)

intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)

{

	return 0;

}

static inline int intel_opregion_get_panel_type(struct drm_device *dev)

static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)

{

	return -ENODEV;

}

drivers/gpu/drm/i915/i915_gem.c

+7 −10
Original line number Diff line number Diff line
@@ -2692,7 +2692,7 @@ void __i915_add_request(struct drm_i915_gem_request *request, 
}



static bool i915_context_is_banned(struct drm_i915_private *dev_priv,

				   const struct intel_context *ctx)

				   const struct i915_gem_context *ctx)

{

	unsigned long elapsed;
@@ -2717,7 +2717,7 @@ static bool i915_context_is_banned(struct drm_i915_private *dev_priv, 
}



static void i915_set_reset_status(struct drm_i915_private *dev_priv,

				  struct intel_context *ctx,

				  struct i915_gem_context *ctx,

				  const bool guilty)

{

	struct i915_ctx_hang_stats *hs;
@@ -2745,7 +2745,7 @@ void i915_gem_request_free(struct kref *req_ref) 


static inline int

__i915_gem_request_alloc(struct intel_engine_cs *engine,

			 struct intel_context *ctx,

			 struct i915_gem_context *ctx,

			 struct drm_i915_gem_request **req_out)

{

	struct drm_i915_private *dev_priv = engine->i915;
@@ -2821,7 +2821,7 @@ err: 
 */

struct drm_i915_gem_request *

i915_gem_request_alloc(struct intel_engine_cs *engine,

		       struct intel_context *ctx)

		       struct i915_gem_context *ctx)

{

	struct drm_i915_gem_request *req;

	int err;
@@ -4886,14 +4886,11 @@ i915_gem_init_hw(struct drm_device *dev) 
	intel_mocs_init_l3cc_table(dev);



	/* We can't enable contexts until all firmware is loaded */

	if (HAS_GUC_UCODE(dev)) {

		ret = intel_guc_ucode_load(dev);

		if (ret) {

			DRM_ERROR("Failed to initialize GuC, error %d\n", ret);

			ret = -EIO;

	if (HAS_GUC(dev)) {

		ret = intel_guc_setup(dev);

		if (ret)

			goto out;

	}

	}



	/*

	 * Increment the next seqno by 0x100 so we have a visible break

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