Commit 5b70a097 authored by John Rigby's avatar John Rigby Committed by Kumar Gala
Browse files

powerpc: 83xx: pci: Remove need for get_immrbase from mpc83xx_add_bridge. 



Modify mpc83xx_add_bridge to get config space register base address from
the device tree instead of immr + hardcoded offset.

83xx pci nodes have this change:
    register properties now contain two address length tuples:
	First is the pci bridge register base, this has always been there.
	Second is the config base, this is new.

This is documented in dts-bindings/fsl/83xx-512x-pci.txt

The changes accomplish these things:
    mpc83xx_add_bridge no longer needs to call get_immrbase
    it uses hard coded addresses if the second register value is missing

Signed-off-by: default avatarJohn Rigby <jrigby@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 4a015c37

Documentation/powerpc/dts-bindings/fsl/83xx-512x-pci.txt

0 → 100644
+40 −0
Original line number Diff line number Diff line 
* Freescale 83xx and 512x PCI bridges



Freescale 83xx and 512x SOCs include the same pci bridge core.



83xx/512x specific notes:

- reg: should contain two address length tuples

    The first is for the internal pci bridge registers

    The second is for the pci config space access registers



Example (MPC8313ERDB)

	pci0: pci@e0008500 {

		cell-index = <1>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

				/* IDSEL 0x0E -mini PCI */

				 0x7000 0x0 0x0 0x1 &ipic 18 0x8

				 0x7000 0x0 0x0 0x2 &ipic 18 0x8

				 0x7000 0x0 0x0 0x3 &ipic 18 0x8

				 0x7000 0x0 0x0 0x4 &ipic 18 0x8



				/* IDSEL 0x0F - PCI slot */

				 0x7800 0x0 0x0 0x1 &ipic 17 0x8

				 0x7800 0x0 0x0 0x2 &ipic 18 0x8

				 0x7800 0x0 0x0 0x3 &ipic 17 0x8

				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;

		interrupt-parent = <&ipic>;

		interrupts = <66 0x8>;

		bus-range = <0x0 0x0>;

		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000

			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;

		clock-frequency = <66666666>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0008500 0x100		/* internal registers */

		       0xe0008300 0x8>;		/* config space access registers */

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

arch/powerpc/boot/dts/mpc8313erdb.dts

+2 −1
Original line number Diff line number Diff line
@@ -363,7 +363,8 @@ 
			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = <0xe0008500 0x100>;

			reg = <0xe0008500 0x100		/* internal registers */

			       0xe0008300 0x8>;		/* config space access registers */

			compatible = "fsl,mpc8349-pci";

			device_type = "pci";

		};

arch/powerpc/boot/dts/mpc8315erdb.dts

+2 −1
Original line number Diff line number Diff line
@@ -318,7 +318,8 @@ 
		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0008500 0x100>;

		reg = <0xe0008500 0x100		/* internal registers */

		       0xe0008300 0x8>;		/* config space access registers */

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

arch/powerpc/boot/dts/mpc832x_mds.dts

+2 −1
Original line number Diff line number Diff line
@@ -423,7 +423,8 @@ 
		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0008500 0x100>;

		reg = <0xe0008500 0x100		/* internal registers */

		       0xe0008300 0x8>;		/* config space access registers */

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

arch/powerpc/boot/dts/mpc832x_rdb.dts

+2 −1
Original line number Diff line number Diff line
@@ -331,7 +331,8 @@ 
		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0008500 0x100>;

		reg = <0xe0008500 0x100		/* internal registers */

		       0xe0008300 0x8>;		/* config space access registers */

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

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