Commit 5b67e8dd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3424/2: ixp23xx: fix uncompress.h for recent CRLF decompressor change
  [ARM] 3434/1: pxa i2s amsl define
  [ARM] 3425/1: xsc3: need to include pgtable-hwdef.h
  [ARM] Allow un-muxed syscalls to be available for everyone
  [ARM] 3420/1: Missing clobber in example code
  [ARM] nommu: fixups for the exception vectors
  [ARM] nommu: add nommu specific Kconfig and MMUEXT variable in Makefile
  [ARM] nommu: start-up code
  [ARM] nommu: MPU support in boot/compressed/head.S
parents a8b59e79 cc3d48db

arch/arm/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -77,6 +77,14 @@ config FIQ 
config ARCH_MTD_XIP

	bool



config VECTORS_BASE

	hex

	default 0xffff0000 if MMU

	default DRAM_BASE if REMAP_VECTORS_TO_RAM

	default 0x00000000

	help

	  The base address of exception vectors.



source "init/Kconfig"



menu "System Type"

arch/arm/Kconfig-nommu

0 → 100644
+44 −0
Original line number Diff line number Diff line 
#

# Kconfig for uClinux(non-paged MM) depend configurations

# Hyok S. Choi <hyok.choi@samsung.com>

# 



config SET_MEM_PARAM

	bool "Set flash/sdram size and base addr"

	help

	 Say Y to manually set the base addresses and sizes.

	 otherwise, the default values are assigned.



config DRAM_BASE

	hex '(S)DRAM Base Address' if SET_MEM_PARAM

	default 0x00800000



config DRAM_SIZE

	hex '(S)DRAM SIZE' if SET_MEM_PARAM

	default 0x00800000



config FLASH_MEM_BASE

	hex 'FLASH Base Address' if SET_MEM_PARAM

	default 0x00400000



config FLASH_SIZE

	hex 'FLASH Size' if SET_MEM_PARAM

	default 0x00400000



config REMAP_VECTORS_TO_RAM

	bool 'Install vectors to the begining of RAM' if DRAM_BASE

	depends on DRAM_BASE

	help

	  The kernel needs to change the hardware exception vectors.

	  In nommu mode, the hardware exception vectors are normally

	  placed at address 0x00000000. However, this region may be

	  occupied by read-only memory depending on H/W design.



	  If the region contains read-write memory, say 'n' here.



	  If your CPU provides a remap facility which allows the exception

	  vectors to be mapped to writable memory, say 'n' here.



	  Otherwise, say 'y' here.  In this case, the kernel will require

	  external support to redirect the hardware exception vectors to

	  the writable versions located at DRAM_BASE.

arch/arm/Makefile

+7 −2
Original line number Diff line number Diff line
@@ -20,6 +20,11 @@ GZFLAGS :=-9 
# Select a platform tht is kept up-to-date

KBUILD_DEFCONFIG := versatile_defconfig



# defines filename extension depending memory manement type.

ifeq ($(CONFIG_MMU),)

MMUEXT		:= -nommu

endif



ifeq ($(CONFIG_FRAME_POINTER),y)

CFLAGS		+=-fno-omit-frame-pointer -mapcs -mno-sched-prolog

endif
@@ -73,7 +78,7 @@ AFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float 
CHECKFLAGS	+= -D__arm__



#Default value

head-y		:= arch/arm/kernel/head.o arch/arm/kernel/init_task.o

head-y		:= arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o

textofs-y	:= 0x00008000



 machine-$(CONFIG_ARCH_RPC)	   := rpc
@@ -133,7 +138,7 @@ else 
MACHINE  :=

endif

  

export	TEXT_OFFSET GZFLAGS

export	TEXT_OFFSET GZFLAGS MMUEXT



# Do we have FASTFPE?

FASTFPE		:=arch/arm/fastfpe

arch/arm/boot/compressed/head.S

+106 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
 *  linux/arch/arm/boot/compressed/head.S

 *

 *  Copyright (C) 1996-2002 Russell King

 *  Copyright (C) 2004 Hyok S. Choi (MPU support)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -320,6 +321,62 @@ params: ldr r0, =params_phys 
cache_on:	mov	r3, #8			@ cache_on function

		b	call_cache_fn



/*

 * Initialize the highest priority protection region, PR7

 * to cover all 32bit address and cacheable and bufferable.

 */

__armv4_mpu_cache_on:

		mov	r0, #0x3f		@ 4G, the whole

		mcr	p15, 0, r0, c6, c7, 0	@ PR7 Area Setting

		mcr 	p15, 0, r0, c6, c7, 1



		mov	r0, #0x80		@ PR7

		mcr	p15, 0, r0, c2, c0, 0	@ D-cache on

		mcr	p15, 0, r0, c2, c0, 1	@ I-cache on

		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on



		mov	r0, #0xc000

		mcr	p15, 0, r0, c5, c0, 1	@ I-access permission

		mcr	p15, 0, r0, c5, c0, 0	@ D-access permission



		mov	r0, #0

		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer

		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache

		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache

		mrc	p15, 0, r0, c1, c0, 0	@ read control reg

						@ ...I .... ..D. WC.M

		orr	r0, r0, #0x002d		@ .... .... ..1. 11.1

		orr	r0, r0, #0x1000		@ ...1 .... .... ....



		mcr	p15, 0, r0, c1, c0, 0	@ write control reg



		mov	r0, #0

		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache

		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache

		mov	pc, lr



__armv3_mpu_cache_on:

		mov	r0, #0x3f		@ 4G, the whole

		mcr	p15, 0, r0, c6, c7, 0	@ PR7 Area Setting



		mov	r0, #0x80		@ PR7

		mcr	p15, 0, r0, c2, c0, 0	@ cache on

		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on



		mov	r0, #0xc000

		mcr	p15, 0, r0, c5, c0, 0	@ access permission



		mov	r0, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mrc	p15, 0, r0, c1, c0, 0	@ read control reg

						@ .... .... .... WC.M

		orr	r0, r0, #0x000d		@ .... .... .... 11.1

		mov	r0, #0

		mcr	p15, 0, r0, c1, c0, 0	@ write control reg



		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mov	pc, lr



__setup_mmu:	sub	r3, r4, #16384		@ Page directory size

		bic	r3, r3, #0xff		@ Align the pointer

		bic	r3, r3, #0x3f00
@@ -496,6 +553,18 @@ proc_types: 
		b	__armv4_mmu_cache_off

		mov	pc, lr



		.word	0x41007400		@ ARM74x

		.word	0xff00ff00

		b	__armv3_mpu_cache_on

		b	__armv3_mpu_cache_off

		b	__armv3_mpu_cache_flush

		

		.word	0x41009400		@ ARM94x

		.word	0xff00ff00

		b	__armv4_mpu_cache_on

		b	__armv4_mpu_cache_off

		b	__armv4_mpu_cache_flush



		.word	0x00007000		@ ARM7 IDs

		.word	0x0000f000

		mov	pc, lr
@@ -562,6 +631,24 @@ proc_types: 
cache_off:	mov	r3, #12			@ cache_off function

		b	call_cache_fn



__armv4_mpu_cache_off:

		mrc	p15, 0, r0, c1, c0

		bic	r0, r0, #0x000d

		mcr	p15, 0, r0, c1, c0	@ turn MPU and cache off

		mov	r0, #0

		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer

		mcr	p15, 0, r0, c7, c6, 0	@ flush D-Cache

		mcr	p15, 0, r0, c7, c5, 0	@ flush I-Cache

		mov	pc, lr



__armv3_mpu_cache_off:

		mrc	p15, 0, r0, c1, c0

		bic	r0, r0, #0x000d

		mcr	p15, 0, r0, c1, c0, 0	@ turn MPU and cache off

		mov	r0, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mov	pc, lr



__armv4_mmu_cache_off:

		mrc	p15, 0, r0, c1, c0

		bic	r0, r0, #0x000d
@@ -601,6 +688,24 @@ cache_clean_flush: 
		mov	r3, #16

		b	call_cache_fn



__armv4_mpu_cache_flush:

		mov	r2, #1

		mov	r3, #0

		mcr	p15, 0, ip, c7, c6, 0	@ invalidate D cache

		mov	r1, #7 << 5		@ 8 segments

1:		orr	r3, r1, #63 << 26	@ 64 entries

2:		mcr	p15, 0, r3, c7, c14, 2	@ clean & invalidate D index

		subs	r3, r3, #1 << 26

		bcs	2b			@ entries 63 to 0

		subs 	r1, r1, #1 << 5

		bcs	1b			@ segments 7 to 0



		teq	r2, #0

		mcrne	p15, 0, ip, c7, c5, 0	@ invalidate I cache

		mcr	p15, 0, ip, c7, c10, 4	@ drain WB

		mov	pc, lr

		



__armv6_mmu_cache_flush:

		mov	r1, #0

		mcr	p15, 0, r1, c7, c14, 0	@ clean+invalidate D
@@ -638,6 +743,7 @@ no_cache_id: 
		mov	pc, lr



__armv3_mmu_cache_flush:

__armv3_mpu_cache_flush:

		mov	r1, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mov	pc, lr

arch/arm/kernel/entry-armv.S

+1 −1
Original line number Diff line number Diff line
@@ -666,7 +666,7 @@ __kuser_helper_start: 
 *

 * #define __kernel_dmb() \

 *         asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \

 *	        : : : "lr","cc" )

 *	        : : : "r0", "lr","cc" )

 */



__kuser_memory_barrier:				@ 0xffff0fa0

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