Commit 5b5bb7c7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v4.21-rockchip-clk-1' of... 

Merge tag 'v4.21-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull rockchip clk driver updates from Heiko Stuebner:

 - register fixes for rk3188 and rk3328
 - one new critical clock for rk3188 and a fixed clock id (double used number)
 - new clock id for rk3328

* tag 'v4.21-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add clock-id to gate of ACODEC for rk3328
  clk: rockchip: add clock ID of ACODEC for rk3328
  clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328
  clk: rockchip: fix I2S1 clock gate register for rk3328
  clk: rockchip: make rk3188 hclk_vio_bus critical
  clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
  clk: rockchip: fix rk3188 sclk_smc gate data
  clk: rockchip: fix typo in rk3188 spdif_frac parent
parents 65102238 d0618247

drivers/clk/rockchip/clk-rk3188.c

+7 −6
Original line number Diff line number Diff line
@@ -362,8 +362,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(2), 5, GFLAGS),

	MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),

	GATE(0, "sclk_mac_lbtest", "sclk_macref",

			RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),

	GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,

			RK2928_CLKGATE_CON(2), 12, GFLAGS),



	COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,

			RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
@@ -382,7 +382,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,

			RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,

			RK2928_CLKGATE_CON(0), 13, GFLAGS),

	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT,

	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(9), 0,

			RK2928_CLKGATE_CON(0), 14, GFLAGS,

			&common_spdif_fracmux),
@@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	 * Clock-Architecture Diagram 4

	 */



	GATE(SCLK_SMC, "sclk_smc", "hclk_peri",

			RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),

	GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,

			RK2928_CLKGATE_CON(2), 4, GFLAGS),



	COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,

			RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
@@ -757,7 +757,8 @@ static const char *const rk3188_critical_clocks[] __initconst = { 
	"hclk_peri",

	"pclk_cpu",

	"pclk_peri",

	"hclk_cpubus"

	"hclk_cpubus",

	"hclk_vio_bus",

};



static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)

drivers/clk/rockchip/clk-rk3328.c

+2 −2
Original line number Diff line number Diff line
@@ -392,7 +392,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKGATE_CON(1), 5, GFLAGS,

			&rk3328_i2s1_fracmux),

	GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,

			RK3328_CLKGATE_CON(0), 6, GFLAGS),

			RK3328_CLKGATE_CON(1), 6, GFLAGS),

	COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,

			RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,

			RK3328_CLKGATE_CON(1), 7, GFLAGS),
@@ -804,7 +804,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),

	GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),

	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),

	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS),

	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),

	GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),

	GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),

	GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),

include/dt-bindings/clock/rk3328-cru.h

+2 −1
Original line number Diff line number Diff line
@@ -172,13 +172,14 @@ 
#define PCLK_HDCP		232

#define PCLK_DCF		233

#define PCLK_SARADC		234

#define PCLK_ACODECPHY		235



/* hclk gates */

#define HCLK_PERI		308

#define HCLK_TSP		309

#define HCLK_GMAC		310

#define HCLK_I2S0_8CH		311

#define HCLK_I2S1_8CH		313

#define HCLK_I2S1_8CH		312

#define HCLK_I2S2_2CH		313

#define HCLK_SPDIF_8CH		314

#define HCLK_VOP		315

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