staging: brcm80211: remove chip simulation specific code (5b5195a5) · Commits · 戴 / test

drivers/staging/brcm80211/brcmsmac/aiutils.h

+0 −2

Original line number	Diff line number	Diff line
		@@ -409,8 +409,6 @@ struct si_pub {
		#define SI_PCIDOWN 2
		#define SI_PCIUP 3

		#define ISSIM_ENAB(sih) 0

		/* PMU clock/power control */
		#if defined(BCMPMUCTL)
		#define PMUCTL_ENAB(sih) (BCMPMUCTL)

+2 −4

Original line number	Diff line number	Diff line
		@@ -5480,10 +5480,8 @@ static void brcms_c_bss_default_init(struct brcms_c_info *wlc)

		/* init default and target BSS with some sane initial values */
		memset((char *)(bi), 0, sizeof(wlc_bss_info_t));
		bi->beacon_period = ISSIM_ENAB(wlc->pub->sih) ? BEACON_INTERVAL_DEF_QT :
		BEACON_INTERVAL_DEFAULT;
		bi->dtim_period = ISSIM_ENAB(wlc->pub->sih) ? DTIM_INTERVAL_DEF_QT :
		DTIM_INTERVAL_DEFAULT;
		bi->beacon_period = BEACON_INTERVAL_DEFAULT;
		bi->dtim_period = DTIM_INTERVAL_DEFAULT;

		/* fill the default channel as the first valid channel
		* starting from the 2G channels

+14 −19

Original line number	Diff line number	Diff line
		@@ -596,8 +596,6 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
		return;

		/* bypass this on QT or VSIM */
		if (!ISSIM_ENAB(sih)) {

		reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
		val16 = R_REG(reg16);

		@@ -611,13 +609,10 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)

		W_REG(reg16, val16);

		pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset,
		&w);
		pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
		w &= ~PCIE_ASPM_ENAB;
		w \|= pi->pcie_war_aspm_ovr;
		pci_write_config_dword(pi->dev,
		pi->pciecap_lcreg_offset, w);
		}
		pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);

		reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
		val16 = R_REG(reg16);

+13 −25

Original line number	Diff line number	Diff line
		@@ -519,6 +519,7 @@ wlc_phy_t wlc_phy_attach(shared_phy_t sh, void *regs, int bandtype,
		phy_info_t *pi;
		u32 sflags = 0;
		uint phyversion;
		u32 idcode;
		int i;

		if (D11REV_IS(sh->corerev, 4))
		@@ -589,12 +590,6 @@ wlc_phy_t wlc_phy_attach(shared_phy_t sh, void *regs, int bandtype,
		}
		}

		if (ISSIM_ENAB(pi->sh->sih)) {
		pi->pubpi.radioid = NORADIO_ID;
		pi->pubpi.radiorev = 5;
		} else {
		u32 idcode;

		wlc_phy_anacore((wlc_phy_t *) pi, ON);

		idcode = wlc_phy_get_radio_ver(pi);
		@@ -604,12 +599,10 @@ wlc_phy_t wlc_phy_attach(shared_phy_t sh, void *regs, int bandtype,
		(idcode & IDCODE_REV_MASK) >> IDCODE_REV_SHIFT;
		pi->pubpi.radiover =
		(idcode & IDCODE_VER_MASK) >> IDCODE_VER_SHIFT;
		if (!VALID_RADIO(pi, pi->pubpi.radioid)) {
		if (!VALID_RADIO(pi, pi->pubpi.radioid))
		goto err;
		}

		wlc_phy_switch_radio((wlc_phy_t *) pi, OFF);
		}

		wlc_set_phy_uninitted(pi);

		@@ -1195,11 +1188,6 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)

		i = 0;
		count = ofdm ? 30 : 250;

		if (ISSIM_ENAB(pi->sh->sih)) {
		count *= 100;
		}

		while ((i++ < count)
		&& (R_REG(&regs->txe_status) & (1 << 7))) {
		udelay(10);

+1 −3

Original line number	Diff line number	Diff line
		@@ -15369,9 +15369,7 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi)
		if (pi->phyhang_avoid)
		wlc_phy_stay_in_carriersearch_nphy(pi, true);

		if (!ISSIM_ENAB(pi->sh->sih)) {
		or_phy_reg(pi, 0xb1, NPHY_IQFlip_ADC1 \| NPHY_IQFlip_ADC2);
		}

		if (NREV_GE(pi->pubpi.phy_rev, 7)) {