Commit 5b4de2f8 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Bjorn Andersson
Browse files

arm64: dts: sdm845: Add qspi opps and power-domains



Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sdm845

Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593769293-6354-3-git-send-email-rnayak@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 54b50f21
Loading
Loading
Loading
Loading
+26 −0
Original line number Diff line number Diff line
@@ -3200,6 +3200,30 @@
			status = "disabled";
		};

		qspi_opp_table: qspi-opp-table {
			compatible = "operating-points-v2";

			opp-19200000 {
				opp-hz = /bits/ 64 <19200000>;
				required-opps = <&rpmhpd_opp_min_svs>;
			};

			opp-100000000 {
				opp-hz = /bits/ 64 <100000000>;
				required-opps = <&rpmhpd_opp_low_svs>;
			};

			opp-150000000 {
				opp-hz = /bits/ 64 <150000000>;
				required-opps = <&rpmhpd_opp_svs>;
			};

			opp-300000000 {
				opp-hz = /bits/ 64 <300000000>;
				required-opps = <&rpmhpd_opp_nom>;
			};
		};

		qspi: spi@88df000 {
			compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
			reg = <0 0x088df000 0 0x600>;
@@ -3209,6 +3233,8 @@
			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
				 <&gcc GCC_QSPI_CORE_CLK>;
			clock-names = "iface", "core";
			power-domains = <&rpmhpd SDM845_CX>;
			operating-points-v2 = <&qspi_opp_table>;
			status = "disabled";
		};