Commit 5b4746a0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "Mostly driver fixes, but there's a core framework fix in here too:

   - Revert the commits that introduce clk management for the SP clk on
     MMP2 SoCs (used for OLPC). Turns out it wasn't a good idea and
     there isn't any need to manage this clk, it just causes more
     headaches.

   - A performance regression that went unnoticed for many years where
     we would traverse the entire clk tree looking for a clk by name
     when we already have the pointer to said clk that we're looking for

   - A parent linkage fix for the qcom SDM845 clk driver

   - An i.MX clk driver rate miscalculation fix where order of
     operations were messed up

   - One error handling fix from the static checkers"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: gcc: Use active only source for CPUSS clocks
  clk: ti: Fix error handling in ti_clk_parse_divider_data()
  clk: imx: Fix fractional clock set rate computation
  clk: Remove global clk traversal on fetch parent index
  Revert "dt-bindings: marvell,mmp2: Add clock id for the SP clock"
  Revert "clk: mmp2: add SP clock"
  Revert "Input: olpc_apsp - enable the SP clock"
parents 52107c54 9ff1a3b4

Documentation/devicetree/bindings/serio/olpc,ap-sp.txt

+0 −4
Original line number Diff line number Diff line
@@ -4,14 +4,10 @@ Required properties: 
- compatible : "olpc,ap-sp"

- reg : base address and length of SoC's WTM registers

- interrupts : SP-AP interrupt

- clocks : phandle + clock-specifier for the clock that drives the WTM

- clock-names:  should be "sp"



Example:

	ap-sp@d4290000 {

		compatible = "olpc,ap-sp";

		reg = <0xd4290000 0x1000>;

		interrupts = <40>;

		clocks = <&soc_clocks MMP2_CLK_SP>;

		clock-names = "sp";

	}

drivers/clk/clk.c

+12 −2
Original line number Diff line number Diff line
@@ -1513,9 +1513,19 @@ static int clk_fetch_parent_index(struct clk_core *core, 
	if (!parent)

		return -EINVAL;



	for (i = 0; i < core->num_parents; i++)

		if (clk_core_get_parent_by_index(core, i) == parent)

	for (i = 0; i < core->num_parents; i++) {

		if (core->parents[i] == parent)

			return i;



		if (core->parents[i])

			continue;



		/* Fallback to comparing globally unique names */

		if (!strcmp(parent->name, core->parent_names[i])) {

			core->parents[i] = parent;

			return i;

		}

	}



	return -EINVAL;

}

drivers/clk/imx/clk-frac-pll.c

+3 −2
Original line number Diff line number Diff line
@@ -155,13 +155,14 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_frac_pll *pll = to_clk_frac_pll(hw);

	u32 val, divfi, divff;

	u64 temp64 = parent_rate;

	u64 temp64;

	int ret;



	parent_rate *= 8;

	rate *= 2;

	divfi = rate / parent_rate;

	temp64 *= rate - divfi;

	temp64 = parent_rate * divfi;

	temp64 = rate - temp64;

	temp64 *= PLL_FRAC_DENOM;

	do_div(temp64, parent_rate);

	divff = temp64;

drivers/clk/mmp/clk-of-mmp2.c

+0 −4
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ 
#define APMU_DISP1	0x110

#define APMU_CCIC0	0x50

#define APMU_CCIC1	0xf4

#define APMU_SP		0x68

#define MPMU_UART_PLL	0x14



struct mmp2_clk_unit {
@@ -210,8 +209,6 @@ static struct mmp_clk_mix_config ccic1_mix_config = { 
	.reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),

};



static DEFINE_SPINLOCK(sp_lock);



static struct mmp_param_mux_clk apmu_mux_clks[] = {

	{MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},

	{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
@@ -242,7 +239,6 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = { 
	{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},

	{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},

	{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},

	{MMP2_CLK_SP, "sp_clk", NULL, CLK_SET_RATE_PARENT, APMU_SP, 0x1b, 0x1b, 0x0, 0, &sp_lock},

};



static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)

drivers/clk/qcom/gcc-sdm845.c

+10 −4
Original line number Diff line number Diff line
@@ -115,8 +115,8 @@ static const char * const gcc_parent_names_6[] = { 
	"core_bi_pll_test_se",

};



static const char * const gcc_parent_names_7[] = {

	"bi_tcxo",

static const char * const gcc_parent_names_7_ao[] = {

	"bi_tcxo_ao",

	"gpll0",

	"gpll0_out_even",

	"core_bi_pll_test_se",
@@ -128,6 +128,12 @@ static const char * const gcc_parent_names_8[] = { 
	"core_bi_pll_test_se",

};



static const char * const gcc_parent_names_8_ao[] = {

	"bi_tcxo_ao",

	"gpll0",

	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_10[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },
@@ -210,7 +216,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 
	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_ahb_clk_src",

		.parent_names = gcc_parent_names_7,

		.parent_names = gcc_parent_names_7_ao,

		.num_parents = 4,

		.ops = &clk_rcg2_ops,

	},
@@ -229,7 +235,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { 
	.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_rbcpr_clk_src",

		.parent_names = gcc_parent_names_8,

		.parent_names = gcc_parent_names_8_ao,

		.num_parents = 3,

		.ops = &clk_rcg2_ops,

	},

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