Unverified Commit 5b4458eb authored Sep 11, 2020 by Miquel Raynal Committed by Mark Brown Sep 21, 2020

ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization



As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.

The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20200911173140.29984-2-miquel.raynal@bootlin.com


Signed-off-by: Mark Brown <broonie@kernel.org>

parent 501ef013

sound/soc/codecs/tlv320aic32x4-clk.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
		if (ret < 0)
		return -EINVAL;

		return clk_aic32x4_pll_set_muldiv(pll, &settings);
		ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
		if (ret)
		return ret;

		/* 10ms is the delay to wait before the clocks are stable */
		msleep(10);

		return 0;
		}

		static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)

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