Commit 5b13ef64 authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
Browse files

clk: meson: clean-up clk81 clocks 



clk81 is a composite clock which parents all the peripheral clocks of the
platform. It is a critical clock which is used as provided by the
bootloader. We don't want to change its rate or reparent it, ever.

Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't
gate so the flag is useless, and the gate is already critical, so the
clock won't ever be unused.

Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is
read-only.

Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for
the divider. A peripheral clock should not try to change the rate of
clk81. Stopping the rate propagation is good way to make sure such request
would be ignored.

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 05f81440

drivers/clk/meson/gxbb.c

+2 −4
Original line number Diff line number Diff line
@@ -775,7 +775,6 @@ static struct clk_regmap gxbb_mpeg_clk_sel = { 
		 */

		.parent_names = clk81_parent_names,

		.num_parents = ARRAY_SIZE(clk81_parent_names),

		.flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),

	},

};
@@ -787,10 +786,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = { 
	},

	.hw.init = &(struct clk_init_data){

		.name = "mpeg_clk_div",

		.ops = &clk_regmap_divider_ops,

		.ops = &clk_regmap_divider_ro_ops,

		.parent_names = (const char *[]){ "mpeg_clk_sel" },

		.num_parents = 1,

		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),

	},

};
@@ -805,7 +803,7 @@ static struct clk_regmap gxbb_clk81 = { 
		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "mpeg_clk_div" },

		.num_parents = 1,

		.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),

		.flags = CLK_IS_CRITICAL,

	},

};

drivers/clk/meson/meson8b.c

+2 −4
Original line number Diff line number Diff line
@@ -506,7 +506,6 @@ static struct clk_regmap meson8b_mpeg_clk_sel = { 
		.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",

			"fclk_div5" },

		.num_parents = 3,

		.flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),

	},

};
@@ -518,10 +517,9 @@ struct clk_regmap meson8b_mpeg_clk_div = { 
	},

	.hw.init = &(struct clk_init_data){

		.name = "mpeg_clk_div",

		.ops = &clk_regmap_divider_ops,

		.ops = &clk_regmap_divider_ro_ops,

		.parent_names = (const char *[]){ "mpeg_clk_sel" },

		.num_parents = 1,

		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),

	},

};
@@ -535,7 +533,7 @@ struct clk_regmap meson8b_clk81 = { 
		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "mpeg_clk_div" },

		.num_parents = 1,

		.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),

		.flags = CLK_IS_CRITICAL,

	},

};

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