Commit 5b0207bb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm-next 

This is the pull request for radeon for 3.11.  Highlights include:

- Support for CIK (Sea Islands) asics: 3D, compute, UVD
- DPM (Dynamic Power Management) support for 6xx-SI
- ASPM support for 6xx-SI
- Assorted bug fixes

* 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux: (168 commits)
  drm/radeon/SI: fix TDP adjustment in set_power_state
  drm/radeon/NI: fix TDP adjustment in set_power_state
  drm/radeon: fix endian issues in atombios dpm code
  drm/radeon/dpm: fix UVD clock setting on SI
  drm/radeon/dpm: fix UVD clock setting on cayman
  drm/radeon/dpm: add support for setting UVD clock on rv6xx
  drm/radeon/dpm: add support for setting UVD clock on rs780
  drm/radeon: fix typo in ni_print_power_state
  drm/radeon: fix typo in cik_select_se_sh()
  drm/radeon/si: fix typo in function name
  drm/radeon/dpm: fix typo in setting uvd clock
  drm/radeon/dpm: add dpm_set_power_state failure output (si)
  add dpm_set_power_state failure output (7xx-ni)
  drm/radeon/dpm: add dpm_set_power_state failure output (7xx-ni)
  drm/radeon/dpm: add dpm_enable failure output (si)
  drm/radeon/dpm: add dpm_enable failure output (7xx-ni)
  drm/radeon/kms: add dpm support for SI (v7)
  drm/radeon: switch SI to use radeon_ucode.h
  drm/radeon: add SI to r600_is_internal_thermal_sensor()
  drm/radeon/dpm/rs780: properly catch errors in dpm setup
  ...
parents 28419261 a144acbc

drivers/gpu/drm/radeon/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -76,7 +76,10 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \

	evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \

	atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \

	si_blit_shaders.o radeon_prime.o radeon_uvd.o

	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/ObjectID.h

+40 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ 
#define ENCODER_OBJECT_ID_ALMOND                  0x22

#define ENCODER_OBJECT_ID_TRAVIS                  0x23

#define ENCODER_OBJECT_ID_NUTMEG                  0x22

#define ENCODER_OBJECT_ID_HDMI_ANX9805            0x26



/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */

#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13

#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
@@ -86,6 +88,8 @@ 
#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1        0x20

#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2        0x21

#define ENCODER_OBJECT_ID_INTERNAL_VCE            0x24

#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY3        0x25

#define ENCODER_OBJECT_ID_INTERNAL_AMCLK          0x27



#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO    0xFF
@@ -364,6 +368,14 @@ 
                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)



#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT)



#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT)



#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
@@ -392,6 +404,10 @@ 
                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT)



#define ENCODER_HDMI_ANX9805_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_HDMI_ANX9805 << OBJECT_ID_SHIFT)



/****************************************************/

/* Connector Object ID definition - Shared with BIOS */

/****************************************************/
@@ -461,6 +477,14 @@ 
                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID5   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID6   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
@@ -473,6 +497,10 @@ 
                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID4     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_VGA_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
@@ -541,6 +569,18 @@ 
                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)



#define CONNECTOR_HDMI_TYPE_A_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)



#define CONNECTOR_HDMI_TYPE_A_ENUM_ID5         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)



#define CONNECTOR_HDMI_TYPE_A_ENUM_ID6         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)



#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)

drivers/gpu/drm/radeon/atombios.h

+511 −36

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/atombios_crtc.c

+79 −9
Original line number Diff line number Diff line
@@ -555,7 +555,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
		if (rdev->family < CHIP_RV770)

			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;

		/* use frac fb div on APUs */

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))

			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

		/* use frac fb div on RS780/RS880 */

		if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
@@ -743,7 +743,7 @@ static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 
			 * SetPixelClock provides the dividers

			 */

			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);

			if (ASIC_IS_DCE61(rdev))

			if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))

				args.v6.ucPpll = ATOM_EXT_PLL1;

			else if (ASIC_IS_DCE6(rdev))

				args.v6.ucPpll = ATOM_PPLL0;
@@ -1143,7 +1143,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	}



	if (tiling_flags & RADEON_TILING_MACRO) {

		if (rdev->family >= CHIP_TAHITI)

		if (rdev->family >= CHIP_BONAIRE)

			tmp = rdev->config.cik.tile_config;

		else if (rdev->family >= CHIP_TAHITI)

			tmp = rdev->config.si.tile_config;

		else if (rdev->family >= CHIP_CAYMAN)

			tmp = rdev->config.cayman.tile_config;
@@ -1170,10 +1172,28 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);

		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);

		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);

		if (rdev->family >= CHIP_BONAIRE) {

			/* XXX need to know more about the surface tiling mode */

			fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);

		}

	} else if (tiling_flags & RADEON_TILING_MICRO)

		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);



	if ((rdev->family == CHIP_TAHITI) ||

	if (rdev->family >= CHIP_BONAIRE) {

		u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;

		u32 num_rb = rdev->config.cik.max_backends_per_se;

		if (num_pipe_configs > 8)

			num_pipe_configs = 8;

		if (num_pipe_configs == 8)

			fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);

		else if (num_pipe_configs == 4) {

			if (num_rb == 4)

				fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);

			else if (num_rb < 4)

				fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);

		} else if (num_pipe_configs == 2)

			fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);

	} else if ((rdev->family == CHIP_TAHITI) ||

		   (rdev->family == CHIP_PITCAIRN))

		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);

	else if (rdev->family == CHIP_VERDE)
@@ -1224,6 +1244,10 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);



	if (rdev->family >= CHIP_BONAIRE)

		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

		       target_fb->height);

	else

		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

		       target_fb->height);

	x &= ~3;
@@ -1597,6 +1621,12 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 
 *

 * Asic specific PLL information

 *

 * DCE 8.x

 * KB/KV

 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)

 * CI

 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC

 *

 * DCE 6.1

 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)

 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
@@ -1623,7 +1653,47 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
	u32 pll_in_use;

	int pll;



	if (ASIC_IS_DCE61(rdev)) {

	if (ASIC_IS_DCE8(rdev)) {

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

			if (rdev->clock.dp_extclk)

				/* skip PPLL programming if using ext clock */

				return ATOM_PPLL_INVALID;

			else {

				/* use the same PPLL for all DP monitors */

				pll = radeon_get_shared_dp_ppll(crtc);

				if (pll != ATOM_PPLL_INVALID)

					return pll;

			}

		} else {

			/* use the same PPLL for all monitors with the same clock */

			pll = radeon_get_shared_nondp_ppll(crtc);

			if (pll != ATOM_PPLL_INVALID)

				return pll;

		}

		/* otherwise, pick one of the plls */

		if ((rdev->family == CHIP_KAVERI) ||

		    (rdev->family == CHIP_KABINI)) {

			/* KB/KV has PPLL1 and PPLL2 */

			pll_in_use = radeon_get_pll_use_mask(crtc);

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

			DRM_ERROR("unable to allocate a PPLL\n");

			return ATOM_PPLL_INVALID;

		} else {

			/* CI has PPLL0, PPLL1, and PPLL2 */

			pll_in_use = radeon_get_pll_use_mask(crtc);

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

			if (!(pll_in_use & (1 << ATOM_PPLL0)))

				return ATOM_PPLL0;

			DRM_ERROR("unable to allocate a PPLL\n");

			return ATOM_PPLL_INVALID;

		}

	} else if (ASIC_IS_DCE61(rdev)) {

		struct radeon_encoder_atom_dig *dig =

			radeon_encoder->enc_priv;
@@ -1861,7 +1931,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) 
		break;

	case ATOM_PPLL0:

		/* disable the ppll */

		if (ASIC_IS_DCE61(rdev))

		if ((rdev->family == CHIP_ARUBA) || (rdev->family == CHIP_BONAIRE))

			atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

						  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);

		break;

drivers/gpu/drm/radeon/atombios_encoders.c

+46 −5
Original line number Diff line number Diff line
@@ -186,6 +186,13 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 
	u8 backlight_level;

	char bl_name[16];



	/* Mac laptops with multiple GPUs use the gmux driver for backlight

	 * so don't register a backlight device

	 */

	if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&

	    (rdev->pdev->device == 0x6741))

		return;



	if (!radeon_encoder->enc_priv)

		return;
@@ -296,6 +303,7 @@ static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

		return true;

	default:

		return false;
@@ -479,11 +487,11 @@ static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 
	}

}





union dvo_encoder_control {

	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;

	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;

	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;

	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;

};



void
@@ -533,6 +541,13 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action) 
			args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);

			args.dvo_v3.ucDVOConfig = 0; /* XXX */

			break;

		case 4:

			/* DCE8 */

			args.dvo_v4.ucAction = action;

			args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);

			args.dvo_v4.ucDVOConfig = 0; /* XXX */

			args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);

			break;

		default:

			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);

			break;
@@ -915,10 +930,14 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo 
				args.v4.ucLaneNum = 4;



			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {

				if (dp_clock == 270000)

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;

				else if (dp_clock == 540000)

				if (dp_clock == 540000)

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;

				else if (dp_clock == 324000)

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;

				else if (dp_clock == 270000)

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;

				else

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;

			}

			args.v4.acConfig.ucDigSel = dig->dig_encoder;

			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
@@ -1012,6 +1031,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t 
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

		index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);

		break;

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
@@ -1271,6 +1291,9 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t 
				else

					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;

				break;

			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

				args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;

				break;

			}

			if (is_dp)

				args.v5.ucLaneNum = dp_lane_count;
@@ -1735,6 +1758,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		radeon_atom_encoder_dpms_dig(encoder, mode);

		break;
@@ -1872,6 +1896,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 
			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

				dig = radeon_encoder->enc_priv;

				switch (dig->dig_encoder) {
@@ -1893,6 +1918,9 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 
				case 5:

					args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;

					break;

				case 6:

					args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;

					break;

				}

				break;

			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
@@ -1955,7 +1983,13 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, 
	/* set scaler clears this on some chips */

	if (ASIC_IS_AVIVO(rdev) &&

	    (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {

		if (ASIC_IS_DCE4(rdev)) {

		if (ASIC_IS_DCE8(rdev)) {

			if (mode->flags & DRM_MODE_FLAG_INTERLACE)

				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,

				       CIK_INTERLEAVE_EN);

			else

				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

		} else if (ASIC_IS_DCE4(rdev)) {

			if (mode->flags & DRM_MODE_FLAG_INTERLACE)

				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,

				       EVERGREEN_INTERLEAVE_EN);
@@ -2002,6 +2036,9 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 
			else

				return 4;

			break;

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

			return 6;

			break;

		}

	} else if (ASIC_IS_DCE4(rdev)) {

		/* DCE4/5 */
@@ -2086,6 +2123,7 @@ radeon_atom_encoder_init(struct radeon_device *rdev) 
		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);

			break;
@@ -2130,6 +2168,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		/* handled in dpms */

		break;
@@ -2395,6 +2434,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		/* handled in dpms */

		break;
@@ -2626,6 +2666,7 @@ radeon_add_atom_encoder(struct drm_device *dev, 
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {

			radeon_encoder->rmx_type = RMX_FULL;

			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);

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