Commit 5af543be authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Temporarily disable 16k pages and hugepages 



In preparation of making use of hardware assistance in TLB handlers,
this patch temporarily disables 16K pages and hugepages. The reason
is that when using HW assistance in 4K pages mode, the linux model
fit with the HW model for 4K pages and 8M pages.

However for 16K pages and 512K mode some additional work is needed
to get linux model fit with HW model.
For the 8M pages, they will naturaly come back when we switch to
HW assistance, without any additional handling.
In order to keep the following patch smaller, the removal of the
current special handling for 8M pages gets removed here as well.

Therefore the 4K pages mode will be implemented first and without
support for 512k hugepages. Then the 512k hugepages will be brought
back. And the 16K pages will be implemented in the following step.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 8cfe4f52

arch/powerpc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -689,7 +689,7 @@ config PPC_4K_PAGES 


config PPC_16K_PAGES

	bool "16k page size"

	depends on 44x || PPC_8xx

	depends on 44x



config PPC_64K_PAGES

	bool "64k page size"

arch/powerpc/kernel/head_8xx.S

+5 −69
Original line number Diff line number Diff line
@@ -314,7 +314,7 @@ SystemCall: 
InstructionTLBMiss:

	mtspr	SPRN_SPRG_SCRATCH0, r10

	mtspr	SPRN_SPRG_SCRATCH1, r11

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)

#ifdef ITLB_MISS_KERNEL

	mtspr	SPRN_SPRG_SCRATCH2, r12

#endif
@@ -325,10 +325,8 @@ InstructionTLBMiss: 
	INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)

	/* Only modules will cause ITLB Misses as we always

	 * pin the first 8MB of kernel memory */

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)

	mfcr	r12

#endif

#ifdef ITLB_MISS_KERNEL

	mfcr	r12

#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)

	andis.	r11, r10, 0x8000	/* Address >= 0x80000000 */

#else
@@ -360,15 +358,9 @@ InstructionTLBMiss: 


	/* Extract level 2 index */

	rlwinm	r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29

#ifdef CONFIG_HUGETLB_PAGE

	mtcr	r11

	bt-	28, 10f		/* bit 28 = Large page (8M) */

	bt-	29, 20f		/* bit 29 = Large page (8M or 512k) */

#endif

	rlwimi	r10, r11, 0, 0, 32 - PAGE_SHIFT - 1	/* Add level 2 base */

	lwz	r10, 0(r10)	/* Get the pte */

4:

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)

#ifdef ITLB_MISS_KERNEL

	mtcr	r12

#endif

	/* Load the MI_TWC with the attributes for this "segment." */
@@ -393,7 +385,7 @@ InstructionTLBMiss: 
	/* Restore registers */

0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)

#ifdef ITLB_MISS_KERNEL

	mfspr	r12, SPRN_SPRG_SCRATCH2

#endif

	rfi
@@ -406,35 +398,12 @@ InstructionTLBMiss: 
	stw	r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)

	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)

#ifdef ITLB_MISS_KERNEL

	mfspr	r12, SPRN_SPRG_SCRATCH2

#endif

	rfi

#endif



#ifdef CONFIG_HUGETLB_PAGE

10:	/* 8M pages */

#ifdef CONFIG_PPC_16K_PAGES

	/* Extract level 2 index */

	rlwinm	r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29

	/* Add level 2 base */

	rlwimi	r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1

#else

	/* Level 2 base */

	rlwinm	r10, r11, 0, ~HUGEPD_SHIFT_MASK

#endif

	lwz	r10, 0(r10)	/* Get the pte */

	b	4b



20:	/* 512k pages */

	/* Extract level 2 index */

	rlwinm	r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29

	/* Add level 2 base */

	rlwimi	r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1

	lwz	r10, 0(r10)	/* Get the pte */

	b	4b

#endif



	. = 0x1200

DataStoreTLBMiss:

	mtspr	SPRN_SPRG_SCRATCH0, r10
@@ -472,11 +441,6 @@ DataStoreTLBMiss: 
	 */

	/* Extract level 2 index */

	rlwinm	r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29

#ifdef CONFIG_HUGETLB_PAGE

	mtcr	r11

	bt-	28, 10f		/* bit 28 = Large page (8M) */

	bt-	29, 20f		/* bit 29 = Large page (8M or 512k) */

#endif

	rlwimi	r10, r11, 0, 0, 32 - PAGE_SHIFT - 1	/* Add level 2 base */

	lwz	r10, 0(r10)	/* Get the pte */

4:
@@ -534,29 +498,6 @@ DataStoreTLBMiss: 
	rfi

#endif



#ifdef CONFIG_HUGETLB_PAGE

10:	/* 8M pages */

	/* Extract level 2 index */

#ifdef CONFIG_PPC_16K_PAGES

	rlwinm	r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29

	/* Add level 2 base */

	rlwimi	r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1

#else

	/* Level 2 base */

	rlwinm	r10, r11, 0, ~HUGEPD_SHIFT_MASK

#endif

	lwz	r10, 0(r10)	/* Get the pte */

	b	4b



20:	/* 512k pages */

	/* Extract level 2 index */

	rlwinm	r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29

	/* Add level 2 base */

	rlwimi	r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1

	lwz	r10, 0(r10)	/* Get the pte */

	b	4b

#endif



/* This is an instruction TLB error on the MPC8xx.  This could be due

 * to many reasons, such as executing guarded memory or illegal instruction

 * addresses.  There is nothing to do but handle a big time error fault.
@@ -773,12 +714,7 @@ FixupDAR:/* Entry point for dcbx workaround. */ 


	/* concat physical page address(r11) and page offset(r10) */

200:

#ifdef CONFIG_PPC_16K_PAGES

	rlwinm	r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1

	rlwimi	r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29

#else

	rlwinm	r11, r10, 0, ~HUGEPD_SHIFT_MASK

#endif

	lwz	r11, 0(r11)	/* Get the pte */

	/* concat physical page address(r11) and page offset(r10) */

	rlwimi	r11, r10, 0, 32 - PAGE_SHIFT_8M, 31

arch/powerpc/mm/tlb_nohash.c

+0 −6
Original line number Diff line number Diff line
@@ -97,12 +97,6 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 
		.shift	= 14,

	},

#endif

	[MMU_PAGE_512K] = {

		.shift	= 19,

	},

	[MMU_PAGE_8M] = {

		.shift	= 23,

	},

};

#else

struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {

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