amd-xgbe: Add I2C support for sideband communication (5ab1dcd5) · Commits · 戴 / test

drivers/net/ethernet/amd/xgbe/Makefile

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -3,7 +3,7 @@ obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o
	amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \		amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
	xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \		xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
	xgbe-ptp.o \		xgbe-ptp.o \
	xgbe-phy-v1.o xgbe-phy-v2.o \		xgbe-i2c.o xgbe-phy-v1.o xgbe-phy-v2.o \
	xgbe-platform.o		xgbe-platform.o

	amd-xgbe-$(CONFIG_PCI) += xgbe-pci.o		amd-xgbe-$(CONFIG_PCI) += xgbe-pci.o

drivers/net/ethernet/amd/xgbe/xgbe-common.h

+92 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1000,6 +1000,65 @@
	#define XP_PROP_2_TX_FIFO_SIZE_INDEX 0		#define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
	#define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16		#define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16

			/* I2C Control register offsets */
			#define IC_CON 0x0000
			#define IC_TAR 0x0004
			#define IC_DATA_CMD 0x0010
			#define IC_INTR_STAT 0x002c
			#define IC_INTR_MASK 0x0030
			#define IC_RAW_INTR_STAT 0x0034
			#define IC_CLR_INTR 0x0040
			#define IC_CLR_TX_ABRT 0x0054
			#define IC_CLR_STOP_DET 0x0060
			#define IC_ENABLE 0x006c
			#define IC_TXFLR 0x0074
			#define IC_RXFLR 0x0078
			#define IC_TX_ABRT_SOURCE 0x0080
			#define IC_ENABLE_STATUS 0x009c
			#define IC_COMP_PARAM_1 0x00f4

			/* I2C Control register entry bit positions and sizes */
			#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
			#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
			#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
			#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
			#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
			#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
			#define IC_CON_MASTER_MODE_INDEX 0
			#define IC_CON_MASTER_MODE_WIDTH 1
			#define IC_CON_RESTART_EN_INDEX 5
			#define IC_CON_RESTART_EN_WIDTH 1
			#define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
			#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
			#define IC_CON_SLAVE_DISABLE_INDEX 6
			#define IC_CON_SLAVE_DISABLE_WIDTH 1
			#define IC_CON_SPEED_INDEX 1
			#define IC_CON_SPEED_WIDTH 2
			#define IC_DATA_CMD_CMD_INDEX 8
			#define IC_DATA_CMD_CMD_WIDTH 1
			#define IC_DATA_CMD_STOP_INDEX 9
			#define IC_DATA_CMD_STOP_WIDTH 1
			#define IC_ENABLE_ABORT_INDEX 1
			#define IC_ENABLE_ABORT_WIDTH 1
			#define IC_ENABLE_EN_INDEX 0
			#define IC_ENABLE_EN_WIDTH 1
			#define IC_ENABLE_STATUS_EN_INDEX 0
			#define IC_ENABLE_STATUS_EN_WIDTH 1
			#define IC_INTR_MASK_TX_EMPTY_INDEX 4
			#define IC_INTR_MASK_TX_EMPTY_WIDTH 1
			#define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
			#define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
			#define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
			#define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
			#define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
			#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
			#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
			#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1

			/* I2C Control register value */
			#define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
			#define IC_TX_ABRT_ARB_LOST 0x1000

	/* Descriptor/Packet entry bit positions and sizes */		/* Descriptor/Packet entry bit positions and sizes */
	#define RX_PACKET_ERRORS_CRC_INDEX 2		#define RX_PACKET_ERRORS_CRC_INDEX 2
	#define RX_PACKET_ERRORS_CRC_WIDTH 1		#define RX_PACKET_ERRORS_CRC_WIDTH 1
	@@ -1469,6 +1528,39 @@ do { \
	XP_IOWRITE((_pdata), (_reg), reg_val); \		XP_IOWRITE((_pdata), (_reg), reg_val); \
	} while (0)		} while (0)

			/* Macros for building, reading or writing register values or bits
			* within the register values of I2C Control registers.
			*/
			#define XI2C_GET_BITS(_var, _prefix, _field) \
			GET_BITS((_var), \
			_prefix##_##_field##_INDEX, \
			_prefix##_##_field##_WIDTH)

			#define XI2C_SET_BITS(_var, _prefix, _field, _val) \
			SET_BITS((_var), \
			_prefix##_##_field##_INDEX, \
			_prefix##_##_field##_WIDTH, (_val))

			#define XI2C_IOREAD(_pdata, _reg) \
			ioread32((_pdata)->xi2c_regs + (_reg))

			#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
			GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
			_reg##_##_field##_INDEX, \
			_reg##_##_field##_WIDTH)

			#define XI2C_IOWRITE(_pdata, _reg, _val) \
			iowrite32((_val), (_pdata)->xi2c_regs + (_reg))

			#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
			do { \
			u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \
			SET_BITS(reg_val, \
			_reg##_##_field##_INDEX, \
			_reg##_##_field##_WIDTH, (_val)); \
			XI2C_IOWRITE((_pdata), (_reg), reg_val); \
			} while (0)

	/* Macros for building, reading or writing register values or bits		/* Macros for building, reading or writing register values or bits
	* using MDIO. Different from above because of the use of standardized		* using MDIO. Different from above because of the use of standardized
	* Linux include values. No shifting is performed with the bit		* Linux include values. No shifting is performed with the bit

drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c

+76 −0

Original line number	Original line	Diff line number	Diff line
	@@ -376,6 +376,66 @@ static const struct file_operations xprop_reg_value_fops = {
	.write = xprop_reg_value_write,		.write = xprop_reg_value_write,
	};		};

			static ssize_t xi2c_reg_addr_read(struct file filp, char __user buffer,
			size_t count, loff_t *ppos)
			{
			struct xgbe_prv_data *pdata = filp->private_data;

			return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xi2c_reg);
			}

			static ssize_t xi2c_reg_addr_write(struct file *filp,
			const char __user *buffer,
			size_t count, loff_t *ppos)
			{
			struct xgbe_prv_data *pdata = filp->private_data;

			return xgbe_common_write(buffer, count, ppos,
			&pdata->debugfs_xi2c_reg);
			}

			static ssize_t xi2c_reg_value_read(struct file filp, char __user buffer,
			size_t count, loff_t *ppos)
			{
			struct xgbe_prv_data *pdata = filp->private_data;
			unsigned int value;

			value = XI2C_IOREAD(pdata, pdata->debugfs_xi2c_reg);

			return xgbe_common_read(buffer, count, ppos, value);
			}

			static ssize_t xi2c_reg_value_write(struct file *filp,
			const char __user *buffer,
			size_t count, loff_t *ppos)
			{
			struct xgbe_prv_data *pdata = filp->private_data;
			unsigned int value;
			ssize_t len;

			len = xgbe_common_write(buffer, count, ppos, &value);
			if (len < 0)
			return len;

			XI2C_IOWRITE(pdata, pdata->debugfs_xi2c_reg, value);

			return len;
			}

			static const struct file_operations xi2c_reg_addr_fops = {
			.owner = THIS_MODULE,
			.open = simple_open,
			.read = xi2c_reg_addr_read,
			.write = xi2c_reg_addr_write,
			};

			static const struct file_operations xi2c_reg_value_fops = {
			.owner = THIS_MODULE,
			.open = simple_open,
			.read = xi2c_reg_value_read,
			.write = xi2c_reg_value_write,
			};

	void xgbe_debugfs_init(struct xgbe_prv_data *pdata)		void xgbe_debugfs_init(struct xgbe_prv_data *pdata)
	{		{
	struct dentry *pfile;		struct dentry *pfile;
	@@ -443,6 +503,22 @@ void xgbe_debugfs_init(struct xgbe_prv_data *pdata)
	"debugfs_create_file failed\n");		"debugfs_create_file failed\n");
	}		}

			if (pdata->xi2c_regs) {
			pfile = debugfs_create_file("xi2c_register", 0600,
			pdata->xgbe_debugfs, pdata,
			&xi2c_reg_addr_fops);
			if (!pfile)
			netdev_err(pdata->netdev,
			"debugfs_create_file failed\n");

			pfile = debugfs_create_file("xi2c_register_value", 0600,
			pdata->xgbe_debugfs, pdata,
			&xi2c_reg_value_fops);
			if (!pfile)
			netdev_err(pdata->netdev,
			"debugfs_create_file failed\n");
			}

	kfree(buf);		kfree(buf);
	}		}

drivers/net/ethernet/amd/xgbe/xgbe-drv.c

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -530,6 +530,10 @@ static irqreturn_t xgbe_isr(int irq, void *data)
	if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))		if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
	xgbe_ecc_isr(irq, pdata);		xgbe_ecc_isr(irq, pdata);

			/* If there is not a separate I2C irq, handle it here */
			if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
			pdata->i2c_if.i2c_isr(irq, pdata);

	isr_done:		isr_done:
	return IRQ_HANDLED;		return IRQ_HANDLED;
	}		}

drivers/net/ethernet/amd/xgbe/xgbe-i2c.c

0 → 100644

+492 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* AMD 10Gb Ethernet driver
			*
			* This file is available to you under your choice of the following two
			* licenses:
			*
			* License 1: GPLv2
			*
			* Copyright (c) 2016 Advanced Micro Devices, Inc.
			*
			* This file is free software; you may copy, redistribute and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 2 of the License, or (at
			* your option) any later version.
			*
			* This file is distributed in the hope that it will be useful, but
			* WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
			* General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/>.
			*
			* This file incorporates work covered by the following copyright and
			* permission notice:
			* The Synopsys DWC ETHER XGMAC Software Driver and documentation
			* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
			* Inc. unless otherwise expressly agreed to in writing between Synopsys
			* and you.
			*
			* The Software IS NOT an item of Licensed Software or Licensed Product
			* under any End User Software License Agreement or Agreement for Licensed
			* Product with Synopsys or any supplement thereto. Permission is hereby
			* granted, free of charge, to any person obtaining a copy of this software
			* annotated with this license and the Software, to deal in the Software
			* without restriction, including without limitation the rights to use,
			* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
			* of the Software, and to permit persons to whom the Software is furnished
			* to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice shall be included
			* in all copies or substantial portions of the Software.
			*
			* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
			* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
			* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
			* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
			* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
			* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
			* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
			* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
			* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
			* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
			* THE POSSIBILITY OF SUCH DAMAGE.
			*
			*
			* License 2: Modified BSD
			*
			* Copyright (c) 2016 Advanced Micro Devices, Inc.
			* All rights reserved.
			*
			* Redistribution and use in source and binary forms, with or without
			* modification, are permitted provided that the following conditions are met:
			* * Redistributions of source code must retain the above copyright
			* notice, this list of conditions and the following disclaimer.
			* * Redistributions in binary form must reproduce the above copyright
			* notice, this list of conditions and the following disclaimer in the
			* documentation and/or other materials provided with the distribution.
			* * Neither the name of Advanced Micro Devices, Inc. nor the
			* names of its contributors may be used to endorse or promote products
			* derived from this software without specific prior written permission.
			*
			* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
			* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
			* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
			* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
			* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
			* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
			* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
			* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
			* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
			*
			* This file incorporates work covered by the following copyright and
			* permission notice:
			* The Synopsys DWC ETHER XGMAC Software Driver and documentation
			* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
			* Inc. unless otherwise expressly agreed to in writing between Synopsys
			* and you.
			*
			* The Software IS NOT an item of Licensed Software or Licensed Product
			* under any End User Software License Agreement or Agreement for Licensed
			* Product with Synopsys or any supplement thereto. Permission is hereby
			* granted, free of charge, to any person obtaining a copy of this software
			* annotated with this license and the Software, to deal in the Software
			* without restriction, including without limitation the rights to use,
			* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
			* of the Software, and to permit persons to whom the Software is furnished
			* to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice shall be included
			* in all copies or substantial portions of the Software.
			*
			* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
			* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
			* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
			* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
			* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
			* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
			* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
			* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
			* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
			* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
			* THE POSSIBILITY OF SUCH DAMAGE.
			*/

			#include <linux/module.h>
			#include <linux/kmod.h>
			#include <linux/delay.h>
			#include <linux/completion.h>
			#include <linux/mutex.h>

			#include "xgbe.h"
			#include "xgbe-common.h"

			#define XGBE_ABORT_COUNT 500
			#define XGBE_DISABLE_COUNT 1000

			#define XGBE_STD_SPEED 1

			#define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
			#define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
			#define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
			#define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
			#define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL \| \
			XGBE_INTR_TX_EMPTY \| \
			XGBE_INTR_TX_ABRT \| \
			XGBE_INTR_STOP_DET)

			#define XGBE_I2C_READ BIT(8)
			#define XGBE_I2C_STOP BIT(9)

			static int xgbe_i2c_abort(struct xgbe_prv_data *pdata)
			{
			unsigned int wait = XGBE_ABORT_COUNT;

			/* Must be enabled to recognize the abort request */
			XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);

			/* Issue the abort */
			XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);

			while (wait--) {
			if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
			return 0;

			usleep_range(500, 600);
			}

			return -EBUSY;
			}

			static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
			{
			unsigned int wait = XGBE_DISABLE_COUNT;
			unsigned int mode = enable ? 1 : 0;

			while (wait--) {
			XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
			if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
			return 0;

			usleep_range(100, 110);
			}

			return -EBUSY;
			}

			static int xgbe_i2c_disable(struct xgbe_prv_data *pdata)
			{
			unsigned int ret;

			ret = xgbe_i2c_set_enable(pdata, false);
			if (ret) {
			/* Disable failed, try an abort */
			ret = xgbe_i2c_abort(pdata);
			if (ret)
			return ret;

			/* Abort succeeded, try to disable again */
			ret = xgbe_i2c_set_enable(pdata, false);
			}

			return ret;
			}

			static int xgbe_i2c_enable(struct xgbe_prv_data *pdata)
			{
			return xgbe_i2c_set_enable(pdata, true);
			}

			static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
			{
			XI2C_IOREAD(pdata, IC_CLR_INTR);
			}

			static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
			{
			XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
			}

			static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
			{
			XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
			}

			static void xgbe_i2c_write(struct xgbe_prv_data *pdata)
			{
			struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
			unsigned int tx_slots;
			unsigned int cmd;

			/* Configured to never receive Rx overflows, so fill up Tx fifo */
			tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
			while (tx_slots && state->tx_len) {
			if (state->op->cmd == XGBE_I2C_CMD_READ)
			cmd = XGBE_I2C_READ;
			else
			cmd = *state->tx_buf++;

			if (state->tx_len == 1)
			XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);

			XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);

			tx_slots--;
			state->tx_len--;
			}

			/* No more Tx operations, so ignore TX_EMPTY and return */
			if (!state->tx_len)
			XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
			}

			static void xgbe_i2c_read(struct xgbe_prv_data *pdata)
			{
			struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
			unsigned int rx_slots;

			/* Anything to be read? */
			if (state->op->cmd != XGBE_I2C_CMD_READ)
			return;

			rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
			while (rx_slots && state->rx_len) {
			*state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
			state->rx_len--;
			rx_slots--;
			}
			}

			static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata,
			unsigned int isr)
			{
			struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;

			if (isr & XGBE_INTR_TX_ABRT) {
			state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
			XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
			}

			if (isr & XGBE_INTR_STOP_DET)
			XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
			}

			static irqreturn_t xgbe_i2c_isr(int irq, void *data)
			{
			struct xgbe_prv_data pdata = (struct xgbe_prv_data )data;
			struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
			unsigned int isr;

			isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
			netif_dbg(pdata, intr, pdata->netdev,
			"I2C interrupt received: status=%#010x\n", isr);

			xgbe_i2c_clear_isr_interrupts(pdata, isr);

			if (isr & XGBE_INTR_TX_ABRT) {
			netif_dbg(pdata, link, pdata->netdev,
			"I2C TX_ABRT received (%#010x) for target %#04x\n",
			state->tx_abort_source, state->op->target);

			xgbe_i2c_disable_interrupts(pdata);

			state->ret = -EIO;
			goto out;
			}

			/* Check for data in the Rx fifo */
			xgbe_i2c_read(pdata);

			/* Fill up the Tx fifo next */
			xgbe_i2c_write(pdata);

			out:
			/* Complete on an error or STOP condition */
			if (state->ret \|\| XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
			complete(&pdata->i2c_complete);

			return IRQ_HANDLED;
			}

			static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
			{
			unsigned int reg;

			reg = XI2C_IOREAD(pdata, IC_CON);
			XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
			XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
			XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
			XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
			XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
			XI2C_IOWRITE(pdata, IC_CON, reg);
			}

			static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
			{
			struct xgbe_i2c *i2c = &pdata->i2c;
			unsigned int reg;

			reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
			i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
			MAX_SPEED_MODE);
			i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
			RX_BUFFER_DEPTH);
			i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
			TX_BUFFER_DEPTH);

			if (netif_msg_probe(pdata))
			dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n",
			"MAX_SPEED_MODE", i2c->max_speed_mode,
			"RX_BUFFER_DEPTH", i2c->rx_fifo_size,
			"TX_BUFFER_DEPTH", i2c->tx_fifo_size);
			}

			static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
			{
			XI2C_IOWRITE(pdata, IC_TAR, addr);
			}

			static irqreturn_t xgbe_i2c_combined_isr(int irq, struct xgbe_prv_data *pdata)
			{
			if (!XI2C_IOREAD(pdata, IC_RAW_INTR_STAT))
			return IRQ_HANDLED;

			return xgbe_i2c_isr(irq, pdata);
			}

			static int xgbe_i2c_xfer(struct xgbe_prv_data pdata, struct xgbe_i2c_op op)
			{
			struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
			int ret;

			mutex_lock(&pdata->i2c_mutex);

			reinit_completion(&pdata->i2c_complete);

			ret = xgbe_i2c_disable(pdata);
			if (ret) {
			netdev_err(pdata->netdev, "failed to disable i2c master\n");
			goto unlock;
			}

			xgbe_i2c_set_target(pdata, op->target);

			memset(state, 0, sizeof(*state));
			state->op = op;
			state->tx_len = op->len;
			state->tx_buf = op->buf;
			state->rx_len = op->len;
			state->rx_buf = op->buf;

			xgbe_i2c_clear_all_interrupts(pdata);
			ret = xgbe_i2c_enable(pdata);
			if (ret) {
			netdev_err(pdata->netdev, "failed to enable i2c master\n");
			goto unlock;
			}

			/* Enabling the interrupts will cause the TX FIFO empty interrupt to
			* fire and begin to process the command via the ISR.
			*/
			xgbe_i2c_enable_interrupts(pdata);

			if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) {
			netdev_err(pdata->netdev, "i2c operation timed out\n");
			ret = -ETIMEDOUT;
			goto disable;
			}

			ret = state->ret;
			if (ret) {
			if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
			ret = -ENOTCONN;
			else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
			ret = -EAGAIN;
			}

			disable:
			xgbe_i2c_disable_interrupts(pdata);
			xgbe_i2c_disable(pdata);

			unlock:
			mutex_unlock(&pdata->i2c_mutex);

			return ret;
			}

			static void xgbe_i2c_stop(struct xgbe_prv_data *pdata)
			{
			if (!pdata->i2c.started)
			return;

			netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n");

			pdata->i2c.started = 0;

			xgbe_i2c_disable_interrupts(pdata);
			xgbe_i2c_disable(pdata);
			xgbe_i2c_clear_all_interrupts(pdata);

			if (pdata->dev_irq != pdata->i2c_irq)
			devm_free_irq(pdata->dev, pdata->i2c_irq, pdata);
			}

			static int xgbe_i2c_start(struct xgbe_prv_data *pdata)
			{
			int ret;

			if (pdata->i2c.started)
			return 0;

			netif_dbg(pdata, link, pdata->netdev, "starting I2C\n");

			/* If we have a separate I2C irq, enable it */
			if (pdata->dev_irq != pdata->i2c_irq) {
			ret = devm_request_irq(pdata->dev, pdata->i2c_irq,
			xgbe_i2c_isr, 0, pdata->i2c_name,
			pdata);
			if (ret) {
			netdev_err(pdata->netdev, "i2c irq request failed\n");
			return ret;
			}
			}

			pdata->i2c.started = 1;

			return 0;
			}

			static int xgbe_i2c_init(struct xgbe_prv_data *pdata)
			{
			int ret;

			xgbe_i2c_disable_interrupts(pdata);

			ret = xgbe_i2c_disable(pdata);
			if (ret) {
			dev_err(pdata->dev, "failed to disable i2c master\n");
			return ret;
			}

			xgbe_i2c_get_features(pdata);

			xgbe_i2c_set_mode(pdata);

			xgbe_i2c_clear_all_interrupts(pdata);

			return 0;
			}

			void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
			{
			i2c_if->i2c_init = xgbe_i2c_init;

			i2c_if->i2c_start = xgbe_i2c_start;
			i2c_if->i2c_stop = xgbe_i2c_stop;

			i2c_if->i2c_xfer = xgbe_i2c_xfer;

			i2c_if->i2c_isr = xgbe_i2c_combined_isr;
			}

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