Commit 5aa91295 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

bus: ti-sysc: Support 16-bit writes too 



We need to also support 16-bit writes for i2c in addition to the reads
when we start configuring the sysconfig register for reset and idle modes.

Note that only i2c revision register has LO and HI registers, so let's
add a check also for 16-bit register read. This change is currently cosmetic
and does not affect anything until we enable the module specific quirk
handling for i2c reset and enable later on.

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 2b2f7def

drivers/bus/ti-sysc.c

+22 −1
Original line number Diff line number Diff line
@@ -100,6 +100,20 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 


static void sysc_write(struct sysc *ddata, int offset, u32 value)

{

	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {

		writew_relaxed(value & 0xffff, ddata->module_va + offset);



		/* Only i2c revision has LO and HI register with stride of 4 */

		if (ddata->offsets[SYSC_REVISION] >= 0 &&

		    offset == ddata->offsets[SYSC_REVISION]) {

			u16 hi = value >> 16;



			writew_relaxed(hi, ddata->module_va + offset + 4);

		}



		return;

	}



	writel_relaxed(value, ddata->module_va + offset);

}
@@ -109,7 +123,14 @@ static u32 sysc_read(struct sysc *ddata, int offset) 
		u32 val;



		val = readw_relaxed(ddata->module_va + offset);

		val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);



		/* Only i2c revision has LO and HI register with stride of 4 */

		if (ddata->offsets[SYSC_REVISION] >= 0 &&

		    offset == ddata->offsets[SYSC_REVISION]) {

			u16 tmp = readw_relaxed(ddata->module_va + offset + 4);



			val |= tmp << 16;

		}



		return val;

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE