Commit 5aa4a395 authored by Padmavathi Venna's avatar Padmavathi Venna Committed by Kukjin Kim
Browse files

ARM: S5PV210: Modified files for SPI consolidation work 



As SPI platform devices are consolidated to plat-samsung, some
corresponding changes are required in the respective machine folder.
Added SPI Setup file for GPIO configurations and platform data
initialization.

Signed-off-by: default avatarPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 25dada97

arch/arm/mach-s5pv210/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC 
	help

	  Common setup code for the camera interfaces.



config S5PV210_SETUP_SPI

	bool

	help

	  Common setup code for SPI GPIO configurations.



menu "S5PC110 Machines"



config MACH_AQUILA

arch/arm/mach-s5pv210/Makefile

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@@ -35,3 +35,4 @@ obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o 
obj-$(CONFIG_S5PV210_SETUP_IDE)		+= setup-ide.o

obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o

obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o

obj-$(CONFIG_S5PV210_SETUP_SPI)		+= setup-spi.o

arch/arm/mach-s5pv210/include/mach/map.h

+2 −0
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@@ -109,6 +109,8 @@ 
#define S3C_PA_RTC			S5PV210_PA_RTC

#define S3C_PA_USB_HSOTG		S5PV210_PA_HSOTG

#define S3C_PA_WDT			S5PV210_PA_WATCHDOG

#define S3C_PA_SPI0			S5PV210_PA_SPI0

#define S3C_PA_SPI1			S5PV210_PA_SPI1



#define S5P_PA_CHIPID			S5PV210_PA_CHIPID

#define S5P_PA_FIMC0			S5PV210_PA_FIMC0

arch/arm/mach-s5pv210/setup-spi.c

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+51 −0
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/* linux/arch/arm/mach-s5pv210/setup-spi.c

 *

 * Copyright (C) 2011 Samsung Electronics Ltd.

 *		http://www.samsung.com/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/gpio.h>

#include <linux/platform_device.h>



#include <plat/gpio-cfg.h>

#include <plat/s3c64xx-spi.h>



#ifdef CONFIG_S3C64XX_DEV_SPI0

struct s3c64xx_spi_info s3c64xx_spi0_pdata = {

	.fifo_lvl_mask	= 0x1ff,

	.rx_lvl_offset	= 15,

	.high_speed	= 1,

	.tx_st_done	= 25,

};



int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)

{

	s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));

	s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);

	s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,

				S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

	return 0;

}

#endif



#ifdef CONFIG_S3C64XX_DEV_SPI1

struct s3c64xx_spi_info s3c64xx_spi1_pdata = {

	.fifo_lvl_mask	= 0x7f,

	.rx_lvl_offset	= 15,

	.high_speed	= 1,

	.tx_st_done	= 25,

};



int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)

{

	s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));

	s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);

	s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,

				S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

	return 0;

}

#endif

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