Commit 5a7f08c2 authored Oct 23, 2019 by Grygorii Strashko Committed by David S. Miller Oct 25, 2019

net: phy: dp83867: enable robust auto-mdix



The link detection timeouts can be observed (or link might not be detected
at all) when dp83867 PHY is configured in manual mode (speed/duplex).

CFG3[9] Robust Auto-MDIX option allows to significantly improve link detection
in case dp83867 is configured in manual mode and reduce link detection
time.
As per DM: "If link partners are configured to operational modes that are
not supported by normal Auto MDI/MDIX mode (like Auto-Neg versus Force
100Base-TX or Force 100Base-TX versus Force 100Base-TX), this Robust Auto
MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock."

Hence, enable this option by default as there are no known reasons
not to do so.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 546b85bb

drivers/net/phy/dp83867.c

+10 −5

Original line number	Diff line number	Diff line
		@@ -95,6 +95,10 @@
		#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
		#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8

		/* CFG3 bits */
		#define DP83867_CFG3_INT_OE BIT(7)
		#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)

		/* CFG4 bits */
		#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)

		@@ -410,12 +414,13 @@ static int dp83867_config_init(struct phy_device *phydev)
		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
		}

		/* Enable Interrupt output INT_OE in CFG3 register */
		if (phy_interrupt_is_valid(phydev)) {
		val = phy_read(phydev, DP83867_CFG3);
		val \|= BIT(7);
		/* Enable Interrupt output INT_OE in CFG3 register */
		if (phy_interrupt_is_valid(phydev))
		val \|= DP83867_CFG3_INT_OE;

		val \|= DP83867_CFG3_ROBUST_AUTO_MDIX;
		phy_write(phydev, DP83867_CFG3, val);
		}

		if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
		dp83867_config_port_mirroring(phydev);

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