Commit 5a62f995 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (72 commits)
  powerpc/pseries: Fix build of topology stuff without CONFIG_NUMA
  powerpc/pseries: Fix VPHN build errors on non-SMP systems
  powerpc/83xx: add mpc8308_p1m DMA controller device-tree node
  powerpc/83xx: add DMA controller to mpc8308 device-tree node
  powerpc/512x: try to free dma descriptors in case of allocation failure
  powerpc/512x: add MPC8308 dma support
  powerpc/512x: fix the hanged dma transfer issue
  powerpc/512x: scatter/gather dma fix
  powerpc/powermac: Make auto-loading of therm_pm72 possible
  of/address: Use propper endianess in get_flags
  powerpc/pci: Use printf extension %pR for struct resource
  powerpc: Remove unnecessary casts of void ptr
  powerpc: Disable VPHN polling during a suspend operation
  powerpc/pseries: Poll VPA for topology changes and update NUMA maps
  powerpc: iommu: Add device name to iommu error printks
  powerpc: Record vma->phys_addr in ioremap()
  powerpc: Update compat_arch_ptrace
  powerpc: Fix PPC_PTRACE_SETHWDEBUG on PPC_BOOK3S
  powerpc/time: printk time stamp init not correct
  powerpc: Minor cleanups for machdep.h
  ...
parents f1d6d6cd 5d7d8072

Documentation/kernel-parameters.txt

+8 −0
Original line number Diff line number Diff line
@@ -403,6 +403,10 @@ and is between 256 and 4096 characters. It is defined in the file 
	bttv.pll=	See Documentation/video4linux/bttv/Insmod-options

	bttv.tuner=	and Documentation/video4linux/bttv/CARDLIST



	bulk_remove=off	[PPC]  This parameter disables the use of the pSeries

			firmware feature for flushing multiple hpte entries

			at a time.



	c101=		[NET] Moxa C101 synchronous serial card



	cachesize=	[BUGS=X86-32] Override level 2 CPU cache size detection.
@@ -1490,6 +1494,10 @@ and is between 256 and 4096 characters. It is defined in the file 
	mtdparts=	[MTD]

			See drivers/mtd/cmdlinepart.c.



	multitce=off	[PPC]  This parameter disables the use of the pSeries

			firmware feature for updating multiple TCE entries

			at a time.



	onenand.bdry=	[HW,MTD] Flex-OneNAND Boundary Configuration



			Format: [die0_boundary][,die0_lock][,die1_boundary][,die1_lock]

Documentation/powerpc/booting-without-of.txt

+2 −2
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ order to avoid the degeneration that had become the ppc32 kernel entry 
point and the way a new platform should be added to the kernel. The

legacy iSeries platform breaks those rules as it predates this scheme,

but no new board support will be accepted in the main tree that

doesn't follows them properly.  In addition, since the advent of the

doesn't follow them properly.  In addition, since the advent of the

arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit

platforms and 32-bit platforms which move into arch/powerpc will be

required to use these rules as well.
@@ -1025,7 +1025,7 @@ dtc source code can be found at 


WARNING: This version is still in early development stage; the

resulting device-tree "blobs" have not yet been validated with the

kernel. The current generated bloc lacks a useful reserve map (it will

kernel. The current generated block lacks a useful reserve map (it will

be fixed to generate an empty one, it's up to the bootloader to fill

it up) among others. The error handling needs work, bugs are lurking,

etc...

Documentation/powerpc/dts-bindings/4xx/cpm.txt

0 → 100644
+52 −0
Original line number Diff line number Diff line 
PPC4xx Clock Power Management (CPM) node



Required properties:

	- compatible		: compatible list, currently only "ibm,cpm"

	- dcr-access-method	: "native"

	- dcr-reg		: < DCR register range >



Optional properties:

	- er-offset		: All 4xx SoCs with a CPM controller have

				  one of two different order for the CPM

				  registers. Some have the CPM registers

				  in the following order (ER,FR,SR). The

				  others have them in the following order

				  (SR,ER,FR). For the second case set

				  er-offset = <1>.

	- unused-units		: specifier consist of one cell. For each

				  bit in the cell, the corresponding bit

				  in CPM will be set to turn off unused

				  devices.

	- idle-doze		: specifier consist of one cell. For each

				  bit in the cell, the corresponding bit

				  in CPM will be set to turn off unused

				  devices. This is usually just CPM[CPU].

	- standby		: specifier consist of one cell. For each

				  bit in the cell, the corresponding bit

				  in CPM will be set on standby and

				  restored on resume.

	- suspend		: specifier consist of one cell. For each

				  bit in the cell, the corresponding bit

				  in CPM will be set on suspend (mem) and

				  restored on resume. Note, for standby

				  and suspend the corresponding bits can

				  be different or the same. Usually for

				  standby only class 2 and 3 units are set.

				  However, the interface does not care.

				  If they are the same, the additional

				  power saving will be seeing if support

				  is available to put the DDR in self

				  refresh mode and any additional power

				  saving techniques for the specific SoC.



Example:

	CPM0: cpm {

		compatible = "ibm,cpm";

		dcr-access-method = "native";

		dcr-reg = <0x160 0x003>;

		er-offset = <0>;

		unused-units = <0x00000100>;

		idle-doze = <0x02000000>;

		standby = <0xfeff0000>;

		suspend = <0xfeff791d>;

};

arch/powerpc/Kconfig

+13 −3
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ config WORD_SIZE 
config ARCH_PHYS_ADDR_T_64BIT

       def_bool PPC64 || PHYS_64BIT



config ARCH_DMA_ADDR_T_64BIT

	def_bool ARCH_PHYS_ADDR_T_64BIT



config MMU

	bool

	default y
@@ -209,7 +212,7 @@ config ARCH_HIBERNATION_POSSIBLE 
config ARCH_SUSPEND_POSSIBLE

	def_bool y

	depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \

		   PPC_85xx || PPC_86xx || PPC_PSERIES

		   PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x



config PPC_DCR_NATIVE

	bool
@@ -595,13 +598,11 @@ config EXTRA_TARGETS 


	  If unsure, leave blank



if !44x || BROKEN

config ARCH_WANTS_FREEZER_CONTROL

	def_bool y

	depends on ADB_PMU



source kernel/power/Kconfig

endif



config SECCOMP

	bool "Enable seccomp to safely compute untrusted bytecode"
@@ -682,6 +683,15 @@ config FSL_PMC 
	  Freescale MPC85xx/MPC86xx power management controller support

	  (suspend/resume). For MPC83xx see platforms/83xx/suspend.c



config PPC4xx_CPM

	bool

	default y

	depends on SUSPEND && (44x || 40x)

	help

	  PPC4xx Clock Power Management (CPM) support (suspend/resume).

	  It also enables support for two different idle states (idle-wait

	  and idle-doze).



config 4xx_SOC

	bool

arch/powerpc/boot/dts/canyonlands.dts

+9 −22
Original line number Diff line number Diff line
@@ -105,6 +105,15 @@ 
		dcr-reg = <0x00c 0x002>;

	};



	CPM0: cpm {

		compatible = "ibm,cpm";

		dcr-access-method = "native";

		dcr-reg = <0x160 0x003>;

		unused-units = <0x00000100>;

		idle-doze = <0x02000000>;

		standby = <0xfeff791d>;

	};



	L2C0: l2c {

		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";

		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
@@ -270,28 +279,6 @@ 
				interrupts = <0x1 0x4>;

			};



			UART2: serial@ef600500 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <0xef600500 0x00000008>;

				virtual-reg = <0xef600500>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				current-speed = <0>; /* Filled in by U-Boot */

				interrupt-parent = <&UIC1>;

				interrupts = <28 0x4>;

			};



			UART3: serial@ef600600 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <0xef600600 0x00000008>;

				virtual-reg = <0xef600600>;

				clock-frequency = <0>; /* Filled in by U-Boot */

				current-speed = <0>; /* Filled in by U-Boot */

				interrupt-parent = <&UIC1>;

				interrupts = <29 0x4>;

			};



			IIC0: i2c@ef600700 {

				compatible = "ibm,iic-460ex", "ibm,iic";

				reg = <0xef600700 0x00000014>;

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