Commit 5a61ef74 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
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powerpc/64s: Support new device tree binding for discovering CPU features 



The ibm,powerpc-cpu-features device tree binding describes CPU features with
ASCII names and extensible compatibility, privilege, and enablement metadata
that allows improved flexibility and compatibility with new hardware.

The interface is described in detail in ibm,powerpc-cpu-features.txt in this
patch.

Currently this code is not enabled by default, and there are no released
firmwares that provide the binding.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 75bda950

Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt

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*** NOTE ***

This document is copied from OPAL firmware

(skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)



There is more complete overview and documentation of features in that

source tree.  All patches and modifications should go there.

************



ibm,powerpc-cpu-features binding

================================



This device tree binding describes CPU features available to software, with

enablement, privilege, and compatibility metadata.



More general description of design and implementation of this binding is

found in design.txt, which also points to documentation of specific features.





/cpus/ibm,powerpc-cpu-features node binding

-------------------------------------------



Node: ibm,powerpc-cpu-features



Description: Container of CPU feature nodes.



The node name must be "ibm,powerpc-cpu-features".



It is implemented as a child of the node "/cpus", but this must not be

assumed by parsers.



The node is optional but should be provided by new OPAL firmware.



Properties:



- compatible

  Usage: required

  Value type: string

  Definition: "ibm,powerpc-cpu-features"



  This compatibility refers to backwards compatibility of the overall

  design with parsers that behave according to these guidelines. This can

  be extended in a backward compatible manner which would not warrant a

  revision of the compatible property.



- isa

  Usage: required

  Value type: <u32>

  Definition:



  isa that the CPU is currently running in. This provides instruction set

  compatibility, less the individual feature nodes. For example, an ISA v3.0

  implementation that lacks the "transactional-memory" cpufeature node

  should not use transactional memory facilities.



  Value corresponds to the "Power ISA Version" multiplied by 1000.

  For example, <3000> corresponds to Version 3.0, <2070> to Version 2.07.

  The minor digit is available for revisions.



- display-name

  Usage: optional

  Value type: string

  Definition:



  A human readable name for the CPU.



/cpus/ibm,powerpc-cpu-features/example-feature node bindings

----------------------------------------------------------------



Each child node of cpu-features represents a CPU feature / capability.



Node: A string describing an architected CPU feature, e.g., "floating-point".



Description: A feature or capability supported by the CPUs.



The name of the node is a human readable string that forms the interface

used to describe features to software. Features are currently documented

in the code where they are implemented in skiboot/core/cpufeatures.c



Presence of the node indicates the feature is available.



Properties:



- isa

  Usage: required

  Value type: <u32>

  Definition:



  First level of the Power ISA that the feature appears in.

  Software should filter out features when constraining the

  environment to a particular ISA version.



  Value is defined similarly to /cpus/features/isa



- usable-privilege

  Usage: required

  Value type: <u32> bit mask

  Definition:

              Bit numbers are LSB0

              bit 0 - PR (problem state / user mode)

              bit 1 - OS (privileged state)

              bit 2 - HV (hypervisor state)

              All other bits reserved and should be zero.



  This property describes the privilege levels and/or software components

  that can use the feature.



  If bit 0 is set, then the hwcap-bit-nr property will exist.





- hv-support

  Usage: optional

  Value type: <u32> bit mask

  Definition:

              Bit numbers are LSB0

              bit 0 -  HFSCR

              All other bits reserved and should be zero.



  This property describes the HV privilege support required to enable the

  feature to lesser privilege levels. If the property does not exist then no

  support is required.



  If no bits are set, the hypervisor must have explicit/custom support for

  this feature.



  If the HFSCR bit is set, then the hfscr-bit-nr property will exist and

  the feature may be enabled by setting this bit in the HFSCR register.





- os-support

  Usage: optional

  Value type: <u32> bit mask

  Definition:

              Bit numbers are LSB0

              bit 0 -  FSCR

              All other bits reserved and should be zero.



  This property describes the OS privilege support required to enable the

  feature to lesser privilege levels. If the property does not exist then no

  support is required.



  If no bits are set, the operating system must have explicit/custom support

  for this feature.



  If the FSCR bit is set, then the fscr-bit-nr property will exist and

  the feature may be enabled by setting this bit in the FSCR register.





- hfscr-bit-nr

  Usage: optional

  Value type: <u32>

  Definition: HFSCR bit position (LSB0)



  This property exists when the hv-support property HFSCR bit is set. This

  property describes the bit number in the HFSCR register that the

  hypervisor must set in order to enable this feature.



  This property also exists if an HFSCR bit corresponds with this feature.

  This makes CPU feature parsing slightly simpler.





- fscr-bit-nr

  Usage: optional

  Value type: <u32>

  Definition: FSCR bit position (LSB0)



  This property exists when the os-support property FSCR bit is set. This

  property describes the bit number in the FSCR register that the

  operating system must set in order to enable this feature.



  This property also exists if an FSCR bit corresponds with this feature.

  This makes CPU feature parsing slightly simpler.





- hwcap-bit-nr

  Usage: optional

  Value type: <u32>

  Definition: Linux ELF AUX vector bit position (LSB0)



  This property may exist when the usable-privilege property value has PR bit set.

  This property describes the bit number that should be set in the ELF AUX

  hardware capability vectors in order to advertise this feature to userspace.

  Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond

  to 0-31 in AT_HWCAP2 vector, and so on.  Missing AT_HWCAPx vectors implies

  that the feature is not enabled or can not be advertised. Operating systems

  may provide a number of unassigned hardware capability bits to allow for new

  features to be advertised.



  Some properties representing features created before this binding are

  advertised to userspace without a one-to-one hwcap bit number may not specify

  this bit. Operating system will handle those bits specifically.  All new

  features usable by userspace will have a hwcap-bit-nr property.





- dependencies

  Usage: optional

  Value type: <prop-encoded-array>

  Definition:



  If this property exists then it is a list of phandles to cpu feature

  nodes that must be enabled for this feature to be enabled.





Example

-------



	/cpus/ibm,powerpc-cpu-features {

		compatible = "ibm,powerpc-cpu-features";



		isa = <3020>;



		darn {

			isa = <3000>;

			usable-privilege = <1 | 2 | 4>;

			hwcap-bit-nr = <xx>;

		};



		scv {

			isa = <3000>;

			usable-privilege = <1 | 2>;

			os-support = <0>;

			hwcap-bit-nr = <xx>;

		};



		stop {

			isa = <3000>;

			usable-privilege = <2 | 4>;

			hv-support = <0>;

			os-support = <0>;

		};



		vsx2 (hypothetical) {

			isa = <3010>;

			usable-privilege = <1 | 2 | 4>;

			hv-support = <0>;

			os-support = <0>;

			hwcap-bit-nr = <xx>;

		};



		vsx2-newinsns {

			isa = <3020>;

			usable-privilege = <1 | 2 | 4>;

			os-support = <1>;

			fscr-bit-nr = <xx>;

			hwcap-bit-nr = <xx>;

			dependencies = <&vsx2>;

		};



	};

arch/powerpc/Kconfig

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@@ -380,6 +380,22 @@ source "arch/powerpc/platforms/Kconfig" 


menu "Kernel options"



config PPC_DT_CPU_FTRS

	bool "Device-tree based CPU feature discovery & setup"

	depends on PPC_BOOK3S_64

	default n

	help

	  This enables code to use a new device tree binding for describing CPU

	  compatibility and features. Saying Y here will attempt to use the new

	  binding if the firmware provides it. Currently only the skiboot

	  firmware provides this binding.

	  If you're not sure say Y.



config PPC_CPUFEATURES_ENABLE_UNKNOWN

	bool "cpufeatures pass through unknown features to guest/userspace"

	depends on PPC_DT_CPU_FTRS

	default y



config HIGHMEM

	bool "High memory support"

	depends on PPC32

arch/powerpc/include/asm/cpu_has_feature.h

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#ifndef __ASM_POWERPC_CPUFEATURES_H

#define __ASM_POWERPC_CPUFEATURES_H

#ifndef __ASM_POWERPC_CPU_HAS_FEATURE_H

#define __ASM_POWERPC_CPU_HAS_FEATURE_H



#ifndef __ASSEMBLY__
@@ -52,4 +52,4 @@ static inline bool cpu_has_feature(unsigned long feature) 
#endif



#endif /* __ASSEMBLY__ */

#endif /* __ASM_POWERPC_CPUFEATURE_H */
 
#endif /* __ASM_POWERPC_CPU_HAS_FEATURE_H */

arch/powerpc/include/asm/cputable.h

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@@ -118,7 +118,9 @@ extern struct cpu_spec *cur_cpu_spec; 


extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;



extern void set_cur_cpu_spec(struct cpu_spec *s);

extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);

extern void identify_cpu_name(unsigned int pvr);

extern void do_feature_fixups(unsigned long value, void *fixup_start,

			      void *fixup_end);

arch/powerpc/include/asm/dt_cpu_ftrs.h

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#ifndef __ASM_POWERPC_DT_CPU_FTRS_H

#define __ASM_POWERPC_DT_CPU_FTRS_H



/*

 *  Copyright 2017, IBM Corporation

 *  cpufeatures is the new way to discover CPU features with /cpus/features

 *  devicetree. This supersedes PVR based discovery ("cputable"), and older

 *  device tree feature advertisement.

 */



#include <linux/types.h>

#include <asm/asm-compat.h>

#include <asm/feature-fixups.h>

#include <uapi/asm/cputable.h>



#ifdef CONFIG_PPC_DT_CPU_FTRS

bool dt_cpu_ftrs_init(void *fdt);

void dt_cpu_ftrs_scan(void);

bool dt_cpu_ftrs_in_use(void);

#else

static inline bool dt_cpu_ftrs_init(void *fdt) { return false; }

static inline void dt_cpu_ftrs_scan(void) { }

static inline bool dt_cpu_ftrs_in_use(void) { return false; }

#endif



#endif /* __ASM_POWERPC_DT_CPU_FTRS_H */

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