Commit 5a602e15 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "No framework updates for the SPI API this time around aside from one
  small fix, just driver improvments.  Some highlights include:

   - New driver support for CSR USP, Mikrotik RB4xx and Zynq GQSPI
     controllers.

   - Modernisation of the OMAP McSPI controller driver, moving it to
     current APIs to enable support for a wider range of client drivers.

   - DMA support for the bcm2835 controller"

* tag 'spi-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (60 commits)
  spi: zynq: Remove execute bit
  spi: atmel: add support to FIFOs
  spi: atmel: update DT bindings documentation
  spi: spi-fsl-dspi: Update DT binding documentation
  spi: pxa2xx: Constify ACPI device ids
  spi: Add support for Zynq Ultrascale+ MPSoC GQSPI controller
  spi: zynq: Add DT bindings documentation for Zynq Ultrascale+ MPSoC GQSPI controller
  spi: fsl-dspi: Use pinctrl PM helpers
  spi: davinci: change the lower limit of pre-scale divider to 1
  spi: spi-fsl-dspi: Change the way of increasing spi_message->actual_length
  spi: spi-fsl-dspi: Enable TCF interrupt mode support
  spi: atmel: add support for the internal chip-select of the spi controller
  spi: spi-pxa2xx: remove legacy PXA DMA bits
  spi: pxa2xx: Make LPSS SPI general register optional
  spi: pxa2xx: Prepare for new Intel LPSS SPI type
  spi: pxa2xx: Differentiate Intel LPSS types
  spi: restore rx/tx_buf in case of unset CONFIG_HAS_DMA
  spi: rspi: Re-do the returning value of qspi_transfer_out_in
  spi: rspi: modify the name of "qspi_trigger_transfer_out_int" function
  spi: orion: Fix extended baud rates for each Armada SoCs
  ...
parents e12bdf0d fda052b0

Documentation/devicetree/bindings/spi/spi-ath79.txt

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Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller



Required properties:

- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.

- reg: Base address and size of the controllers memory area

- clocks: phandle to the AHB clock.

- clock-names: has to be "ahb".

- #address-cells: <1>, as required by generic SPI binding.

- #size-cells: <0>, also as required by generic SPI binding.



Child nodes as per the generic SPI binding.



Example:



	spi@1F000000 {

		compatible = "qca,ar9132-spi", "qca,ar7100-spi";

		reg = <0x1F000000 0x10>;



		clocks = <&pll 2>;

		clock-names = "ahb";



		#address-cells = <1>;

		#size-cells = <0>;

	};

Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt

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ARM Freescale DSPI controller



Required properties:

- compatible : "fsl,vf610-dspi"

- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"

- reg : Offset and length of the register set for the device

- interrupts : Should contain SPI controller interrupt

- clocks: from common clock binding: handle to dspi clock.

Documentation/devicetree/bindings/spi/spi-orion.txt

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Marvell Orion SPI device



Required properties:

- compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi".

- compatible : should be on of the following:

    - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs

    - "marvell,armada-370-spi", for the Armada 370 SoCs

    - "marvell,armada-375-spi", for the Armada 375 SoCs

    - "marvell,armada-380-spi", for the Armada 38x SoCs

    - "marvell,armada-390-spi", for the Armada 39x SoCs

    - "marvell,armada-xp-spi", for the Armada XP SoCs

- reg : offset and length of the register set for the device

- cell-index : Which of multiple SPI controllers is this.

Optional properties:

Documentation/devicetree/bindings/spi/spi-sirf.txt

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* CSR SiRFprimaII Serial Peripheral Interface



Required properties:

- compatible : Should be "sirf,prima2-spi"

- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp"

               or "sirf,atlas7-usp"

- reg : Offset and length of the register set for the device

- interrupts : Should contain SPI interrupt

- resets: phandle to the reset controller asserting this device in

Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt

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Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings

-------------------------------------------------------------------



Required properties:

- compatible		: Should be "xlnx,zynqmp-qspi-1.0".

- reg			: Physical base address and size of GQSPI registers map.

- interrupts		: Property with a value describing the interrupt

			  number.

- interrupt-parent	: Must be core interrupt controller.

- clock-names		: List of input clock names - "ref_clk", "pclk"

			  (See clock bindings for details).

- clocks		: Clock phandles (see clock bindings for details).



Optional properties:

- num-cs		: Number of chip selects used.



Example:

	qspi: spi@ff0f0000 {

		compatible = "xlnx,zynqmp-qspi-1.0";

		clock-names = "ref_clk", "pclk";

		clocks = <&misc_clk &misc_clk>;

		interrupts = <0 15 4>;

		interrupt-parent = <&gic>;

		num-cs = <1>;

		reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;

	};

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