Merge branch 'Allow-unknown-unicast-traffic-to-CPU-for-Felix-DSA' (5a1c63f1) · Commits · 戴 / test

drivers/net/dsa/ocelot/felix.c

+13 −3

Original line number	Diff line number	Diff line
		@@ -516,12 +516,22 @@ static int felix_setup(struct dsa_switch *ds)
		for (port = 0; port < ds->num_ports; port++) {
		ocelot_init_port(ocelot, port);

		/* Bring up the CPU port module and configure the NPI port */
		if (dsa_is_cpu_port(ds, port))
		ocelot_set_cpu_port(ocelot, port,
		ocelot_configure_cpu(ocelot, port,
		OCELOT_TAG_PREFIX_NONE,
		OCELOT_TAG_PREFIX_LONG);
		}

		/* Include the CPU port module in the forwarding mask for unknown
		* unicast - the hardware default value for ANA_FLOODING_FLD_UNICAST
		* excludes BIT(ocelot->num_phys_ports), and so does ocelot_init, since
		* Ocelot relies on whitelisting MAC addresses towards PGID_CPU.
		*/
		ocelot_write_rix(ocelot,
		ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
		ANA_PGID_PGID, PGID_UC);

		/* It looks like the MAC/PCS interrupt register - PM0_IEVENT (0x8040)
		* isn't instantiated for the Felix PF.
		* In-band AN may take a few ms to complete, so we need to poll.

drivers/net/ethernet/mscc/ocelot.c

+36 −26

Original line number	Diff line number	Diff line
		@@ -1413,7 +1413,7 @@ void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
		* a source for the other ports.
		*/
		for (p = 0; p < ocelot->num_phys_ports; p++) {
		if (p == ocelot->cpu \|\| (ocelot->bridge_fwd_mask & BIT(p))) {
		if (ocelot->bridge_fwd_mask & BIT(p)) {
		unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);

		for (i = 0; i < ocelot->num_phys_ports; i++) {
		@@ -1428,18 +1428,10 @@ void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
		}
		}

		/* Avoid the NPI port from looping back to itself */
		if (p != ocelot->cpu)
		mask \|= BIT(ocelot->cpu);

		ocelot_write_rix(ocelot, mask,
		ANA_PGID_PGID, PGID_SRC + p);
		} else {
		/* Only the CPU port, this is compatible with link
		* aggregation.
		*/
		ocelot_write_rix(ocelot,
		BIT(ocelot->cpu),
		ocelot_write_rix(ocelot, 0,
		ANA_PGID_PGID, PGID_SRC + p);
		}
		}
		@@ -2308,27 +2300,34 @@ int ocelot_probe_port(struct ocelot *ocelot, u8 port,
		}
		EXPORT_SYMBOL(ocelot_probe_port);

		void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
		/* Configure and enable the CPU port module, which is a set of queues.
		* If @npi contains a valid port index, the CPU port module is connected
		* to the Node Processor Interface (NPI). This is the mode through which
		* frames can be injected from and extracted to an external CPU,
		* over Ethernet.
		*/
		void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
		enum ocelot_tag_prefix injection,
		enum ocelot_tag_prefix extraction)
		{
		/* Configure and enable the CPU port. */
		int cpu = ocelot->num_phys_ports;

		/* The unicast destination PGID for the CPU port module is unused */
		ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
		/* Instead set up a multicast destination PGID for traffic copied to
		* the CPU. Whitelisted MAC addresses like the port netdevice MAC
		* addresses will be copied to the CPU via this PGID.
		*/
		ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
		ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA \|
		ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
		ANA_PORT_PORT_CFG, cpu);

		/* If the CPU port is a physical port, set up the port in Node
		* Processor Interface (NPI) mode. This is the mode through which
		* frames can be injected from and extracted to an external CPU.
		* Only one port can be an NPI at the same time.
		*/
		if (cpu < ocelot->num_phys_ports) {
		if (npi >= 0 && npi < ocelot->num_phys_ports) {
		int mtu = VLAN_ETH_FRAME_LEN + OCELOT_TAG_LEN;

		ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M \|
		QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
		QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi),
		QSYS_EXT_CPU_CFG);

		if (injection == OCELOT_TAG_PREFIX_SHORT)
		@@ -2336,14 +2335,27 @@ void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
		else if (injection == OCELOT_TAG_PREFIX_LONG)
		mtu += OCELOT_LONG_PREFIX_LEN;

		ocelot_port_set_mtu(ocelot, cpu, mtu);
		ocelot_port_set_mtu(ocelot, npi, mtu);

		/* Enable NPI port */
		ocelot_write_rix(ocelot,
		QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE \|
		QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) \|
		QSYS_SWITCH_PORT_MODE_PORT_ENA,
		QSYS_SWITCH_PORT_MODE, npi);
		/* NPI port Injection/Extraction configuration */
		ocelot_write_rix(ocelot,
		SYS_PORT_MODE_INCL_XTR_HDR(extraction) \|
		SYS_PORT_MODE_INCL_INJ_HDR(injection),
		SYS_PORT_MODE, npi);
		}

		/* CPU port Injection/Extraction configuration */
		/* Enable CPU port module */
		ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE \|
		QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) \|
		QSYS_SWITCH_PORT_MODE_PORT_ENA,
		QSYS_SWITCH_PORT_MODE, cpu);
		/* CPU port Injection/Extraction configuration */
		ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) \|
		SYS_PORT_MODE_INCL_INJ_HDR(injection),
		SYS_PORT_MODE, cpu);
		@@ -2353,10 +2365,8 @@ void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
		ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA \|
		ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
		ANA_PORT_VLAN_CFG, cpu);

		ocelot->cpu = cpu;
		}
		EXPORT_SYMBOL(ocelot_set_cpu_port);
		EXPORT_SYMBOL(ocelot_configure_cpu);

		int ocelot_init(struct ocelot *ocelot)
		{

drivers/net/ethernet/mscc/ocelot.h

+0 −10

Original line number	Diff line number	Diff line
		@@ -28,16 +28,6 @@
		#include "ocelot_tc.h"
		#include "ocelot_ptp.h"

		#define PGID_AGGR 64
		#define PGID_SRC 80

		/* Reserved PGIDs */
		#define PGID_CPU (PGID_AGGR - 5)
		#define PGID_UC (PGID_AGGR - 4)
		#define PGID_MC (PGID_AGGR - 3)
		#define PGID_MCIPV4 (PGID_AGGR - 2)
		#define PGID_MCIPV6 (PGID_AGGR - 1)

		#define OCELOT_BUFFER_CELL_SZ 60

		#define OCELOT_STATS_CHECK_DELAY (2 * HZ)

drivers/net/ethernet/mscc/ocelot_board.c

+3 −4

Original line number	Diff line number	Diff line
		@@ -453,8 +453,6 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
		ocelot->ptp = 1;
		}

		ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */

		ports = of_get_child_by_name(np, "ethernet-ports");
		if (!ports) {
		dev_err(&pdev->dev, "no ethernet-ports child node found\n");
		@@ -471,8 +469,9 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
		ocelot->vcap = vsc7514_vcap_props;

		ocelot_init(ocelot);
		ocelot_set_cpu_port(ocelot, ocelot->num_phys_ports,
		OCELOT_TAG_PREFIX_NONE, OCELOT_TAG_PREFIX_NONE);
		/* No NPI port */
		ocelot_configure_cpu(ocelot, -1, OCELOT_TAG_PREFIX_NONE,
		OCELOT_TAG_PREFIX_NONE);

		for_each_available_child_of_node(ports, portnp) {
		struct ocelot_port_private *priv;

include/soc/mscc/ocelot.h

+67 −5

Original line number	Diff line number	Diff line
		@@ -11,6 +11,66 @@
		#include <linux/regmap.h>
		#include <net/dsa.h>

		/* Port Group IDs (PGID) are masks of destination ports.
		*
		* For L2 forwarding, the switch performs 3 lookups in the PGID table for each
		* frame, and forwards the frame to the ports that are present in the logical
		* AND of all 3 PGIDs.
		*
		* These PGID lookups are:
		* - In one of PGID[0-63]: for the destination masks. There are 2 paths by
		* which the switch selects a destination PGID:
		* - The {DMAC, VID} is present in the MAC table. In that case, the
		* destination PGID is given by the DEST_IDX field of the MAC table entry
		* that matched.
		* - The {DMAC, VID} is not present in the MAC table (it is unknown). The
		* frame is disseminated as being either unicast, multicast or broadcast,
		* and according to that, the destination PGID is chosen as being the
		* value contained by ANA_FLOODING_FLD_UNICAST,
		* ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
		* The destination PGID can be an unicast set: the first PGIDs, 0 to
		* ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
		* ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
		* a physical port and has a single bit set in the destination ports mask:
		* that corresponding to the port number itself. In contrast, a multicast
		* PGID will have potentially more than one single bit set in the destination
		* ports mask.
		* - In one of PGID[64-79]: for the aggregation mask. The switch classifier
		* dissects each frame and generates a 4-bit Link Aggregation Code which is
		* used for this second PGID table lookup. The goal of link aggregation is to
		* hash multiple flows within the same LAG on to different destination ports.
		* The first lookup will result in a PGID with all the LAG members present in
		* the destination ports mask, and the second lookup, by Link Aggregation
		* Code, will ensure that each flow gets forwarded only to a single port out
		* of that mask (there are no duplicates).
		* - In one of PGID[80-90]: for the source mask. The third time, the PGID table
		* is indexed with the ingress port (plus 80). These PGIDs answer the
		* question "is port i allowed to forward traffic to port j?" If yes, then
		* BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
		* to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
		*/

		/* Reserve some destination PGIDs at the end of the range:
		* PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
		* of the switch port net devices, towards the CPU port module.
		* PGID_UC: the flooding destinations for unknown unicast traffic.
		* PGID_MC: the flooding destinations for broadcast and non-IP multicast
		* traffic.
		* PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
		* PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
		*/
		#define PGID_CPU 59
		#define PGID_UC 60
		#define PGID_MC 61
		#define PGID_MCIPV4 62
		#define PGID_MCIPV6 63

		/* Aggregation PGIDs, one per Link Aggregation Code */
		#define PGID_AGGR 64

		/* Source PGIDs, one per physical port */
		#define PGID_SRC 80

		#define IFH_INJ_BYPASS BIT(31)
		#define IFH_INJ_POP_CNT_DISABLE (3 << 28)

		@@ -451,9 +511,11 @@ struct ocelot {
		/* Keep track of the vlan port masks */
		u32 vlan_mask[VLAN_N_VID];

		/* In tables like ANA:PORT and the ANA:PGID:PGID mask,
		* the CPU is located after the physical ports (at the
		* num_phys_ports index).
		*/
		u8 num_phys_ports;
		u8 num_cpu_ports;
		u8 cpu;

		u32 *lags;

		@@ -508,7 +570,7 @@ void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
		int ocelot_regfields_init(struct ocelot *ocelot,
		const struct reg_field *const regfields);
		struct regmap ocelot_regmap_init(struct ocelot ocelot, struct resource *res);
		void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
		void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
		enum ocelot_tag_prefix injection,
		enum ocelot_tag_prefix extraction);
		int ocelot_init(struct ocelot *ocelot);

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