Commit 59fc8cde authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amd/pp: Move DPMTABLE_* definitions to common header file

parent ee85c07a
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+0 −5
Original line number Diff line number Diff line
@@ -34,11 +34,6 @@
#define SMU7_VOLTAGE_CONTROL_BY_SVID2               0x2
#define SMU7_VOLTAGE_CONTROL_MERGED                 0x3

#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
#define DPMTABLE_UPDATE_SCLK        0x00000004
#define DPMTABLE_UPDATE_MCLK        0x00000008

enum gpu_pt_config_reg_type {
	GPU_CONFIGREG_MMR = 0,
	GPU_CONFIGREG_SMC_IND,
+0 −6
Original line number Diff line number Diff line
@@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
	uint32_t    dcef_clock;
};

#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
#define DPMTABLE_UPDATE_SCLK        0x00000004
#define DPMTABLE_UPDATE_MCLK        0x00000008
#define DPMTABLE_OD_UPDATE_VDDC     0x00000010

struct vega10_smc_state_table {
	uint32_t        soc_boot_level;
	uint32_t        gfx_boot_level;
+11 −0
Original line number Diff line number Diff line
@@ -358,6 +358,17 @@ struct phm_clocks {
	uint32_t clock[MAX_NUM_CLOCKS];
};

#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
#define DPMTABLE_UPDATE_SCLK        0x00000004
#define DPMTABLE_UPDATE_MCLK        0x00000008
#define DPMTABLE_OD_UPDATE_VDDC     0x00000010

/* To determine if sclk and mclk are in overdrive state */
#define SCLK_OVERDRIVE_ENABLED           0x00000001
#define MCLK_OVERDRIVE_ENABLED           0x00000002
#define VDDC_OVERDRIVE_ENABLED           0x00000010

struct phm_odn_performance_level {
	uint32_t clock;
	uint32_t vddc;