Merge tag 'drm-msm-next-2020-03-22' of https://gitlab.freedesktop.org/drm/msm into drm-next

Qualcomm adreno/snapdragon GMU (Graphics management unit)

The GMU is a programmable power controller for the GPU. the CPU controls the

GMU which in turn handles power controls for the GPU.

Required properties:

- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"

    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"

  Note that you need to list the less specific "qcom,adreno-gmu"

  for generic matches and the more specific identifier to identify

  the specific device.

- reg: Physical base address and length of the GMU registers.

- reg-names: Matching names for the register regions

  * "gmu"

  * "gmu_pdc"

  * "gmu_pdc_seg"

- interrupts: The interrupt signals from the GMU.

- interrupt-names: Matching names for the interrupts

  * "hfi"

  * "gmu"

- clocks: phandles to the device clocks

- clock-names: Matching names for the clocks

   * "gmu"

   * "cxo"

   * "axi"

   * "mnoc"

- power-domains: should be:

	<&clock_gpucc GPU_CX_GDSC>

	<&clock_gpucc GPU_GX_GDSC>

- power-domain-names: Matching names for the power domains

- iommus: phandle to the adreno iommu

- operating-points-v2: phandle to the OPP operating points

Optional properties:

- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon

        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

Example:

/ {

	...

	gmu: gmu@506a000 {

		compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

		reg = <0x506a000 0x30000>,

			<0xb280000 0x10000>,

			<0xb480000 0x10000>;

		reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hfi", "gmu";

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

			<&gpucc GPU_CC_CXO_CLK>,

			<&gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&gcc GCC_GPU_MEMNOC_GFX_CLK>;

		clock-names = "gmu", "cxo", "axi", "memnoc";

		power-domains = <&gpucc GPU_CX_GDSC>,

				<&gpucc GPU_GX_GDSC>;

		power-domain-names = "cx", "gx";

		iommus = <&adreno_smmu 5>;

		operating-points-v2 = <&gmu_opp_table>;

	};

};

a3xx example with OCMEM support:

/ {

	...

	gpu: adreno@fdb00000 {

		compatible = "qcom,adreno-330.2",

		             "qcom,adreno";

		reg = <0xfdb00000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";

		clock-names = "core",

		              "iface",

		              "mem_iface";

		clocks = <&mmcc OXILI_GFX3D_CLK>,

		         <&mmcc OXILICX_AHB_CLK>,

		         <&mmcc OXILICX_AXI_CLK>;

		sram = <&gmu_sram>;

		power-domains = <&mmcc OXILICX_GDSC>;

		operating-points-v2 = <&gpu_opp_table>;

		iommus = <&gpu_iommu 0>;

	};

	ocmem@fdd00000 {

		compatible = "qcom,msm8974-ocmem";

		reg = <0xfdd00000 0x2000>,

		      <0xfec00000 0x180000>;

		reg-names = "ctrl",

		             "mem";

		clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,

		         <&mmcc OCMEMCX_OCMEMNOC_CLK>;

		clock-names = "core",

		              "iface";

		#address-cells = <1>;

		#size-cells = <1>;

		gmu_sram: gmu-sram@0 {

			reg = <0x0 0x100000>;

			ranges = <0 0 0xfec00000 0x100000>;

		};

	};

};

# SPDX-License-Identifier: GPL-2.0-only

# Copyright 2019-2020, The Linux Foundation, All Rights Reserved

%YAML 1.2

---

$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Devicetree bindings for the GMU attached to certain Adreno GPUs

maintainers:

  - Rob Clark <robdclark@gmail.com>

description: |

  These bindings describe the Graphics Management Unit (GMU) that is attached

  to members of the Adreno A6xx GPU family. The GMU provides on-device power

  management and support to improve power efficiency and reduce the load on

  the CPU.

properties:

  compatible:

    items:

      - enum:

          - qcom,adreno-gmu-630.2

      - const: qcom,adreno-gmu

  reg:

    items:

      - description: Core GMU registers

      - description: GMU PDC registers

      - description: GMU PDC sequence registers

  reg-names:

    items:

      - const: gmu

      - const: gmu_pdc

      - const: gmu_pdc_seq

  clocks:

    items:

     - description: GMU clock

     - description: GPU CX clock

     - description: GPU AXI clock

     - description: GPU MEMNOC clock

  clock-names:

    items:

      - const: gmu

      - const: cxo

      - const: axi

      - const: memnoc

  interrupts:

    items:

     - description: GMU HFI interrupt

     - description: GMU interrupt

  interrupt-names:

    items:

      - const: hfi

      - const: gmu

  power-domains:

     items:

       - description: CX power domain

       - description: GX power domain

  power-domain-names:

     items:

       - const: cx

       - const: gx

  iommus:

    maxItems: 1

  operating-points-v2: true

required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - power-domains

  - power-domain-names

  - iommus

  - operating-points-v2

examples:

 - |

   #include <dt-bindings/clock/qcom,gpucc-sdm845.h>

   #include <dt-bindings/clock/qcom,gcc-sdm845.h>

   #include <dt-bindings/interrupt-controller/irq.h>

   #include <dt-bindings/interrupt-controller/arm-gic.h>

   gmu: gmu@506a000 {

        compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

        reg = <0x506a000 0x30000>,

              <0xb280000 0x10000>,

              <0xb480000 0x10000>;

        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

                 <&gpucc GPU_CC_CXO_CLK>,

                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;

        clock-names = "gmu", "cxo", "axi", "memnoc";

        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "hfi", "gmu";

        power-domains = <&gpucc GPU_CX_GDSC>,

                        <&gpucc GPU_GX_GDSC>;

        power-domain-names = "cx", "gx";

        iommus = <&adreno_smmu 5>;

        operating-points-v2 = <&gmu_opp_table>;

   };

  bring the GPU out of secure mode.

- firmware-name: optional property of the 'zap-shader' node, listing the

  relative path of the device specific zap firmware.

- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and

        a4xx Snapdragon SoCs. See

        Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

Example 3xx/4xx/a5xx:

Example 3xx/4xx:

/ {

	...

	gpu: qcom,kgsl-3d0@4300000 {

		compatible = "qcom,adreno-320.2", "qcom,adreno";

		reg = <0x04300000 0x20000>;

	gpu: adreno@fdb00000 {

		compatible = "qcom,adreno-330.2",

		             "qcom,adreno";

		reg = <0xfdb00000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <GIC_SPI 80 0>;

		clock-names =

		    "core",

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";

		clock-names = "core",

		              "iface",

		              "mem_iface";

		clocks =

		    <&mmcc GFX3D_CLK>,

		    <&mmcc GFX3D_AHB_CLK>,

		    <&mmcc MMSS_IMEM_AHB_CLK>;

		clocks = <&mmcc OXILI_GFX3D_CLK>,

		         <&mmcc OXILICX_AHB_CLK>,

		         <&mmcc OXILICX_AXI_CLK>;

		sram = <&gpu_sram>;

		power-domains = <&mmcc OXILICX_GDSC>;

		operating-points-v2 = <&gpu_opp_table>;

		iommus = <&gpu_iommu 0>;

	};

	gpu_sram: ocmem@fdd00000 {

		compatible = "qcom,msm8974-ocmem";

		reg = <0xfdd00000 0x2000>,

		      <0xfec00000 0x180000>;

		reg-names = "ctrl",

		            "mem";

		clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,

		         <&mmcc OCMEMCX_OCMEMNOC_CLK>;

		clock-names = "core",

		              "iface";

		#address-cells = <1>;

		#size-cells = <1>;

		gpu_sram: gpu-sram@0 {

			reg = <0x0 0x100000>;

			ranges = <0 0 0xfec00000 0x100000>;

		};

	};

};

static void check_speed_bin(struct device *dev)

{

	struct nvmem_cell *cell;

	u32 bin, val;

	u32 val;

	/*

	 * If the OPP table specifies a opp-supported-hw property then we have

	 * to set something with dev_pm_opp_set_supported_hw() or the table

	 * doesn't get populated so pick an arbitrary value that should

	 * ensure the default frequencies are selected but not conflict with any

	 * actual bins

	 */

	val = 0x80;

	cell = nvmem_cell_get(dev, "speed_bin");

	/* If a nvmem cell isn't defined, nothing to do */

	if (IS_ERR(cell))

		return;

	if (!IS_ERR(cell)) {

		void *buf = nvmem_cell_read(cell, NULL);

	bin = *((u32 *) nvmem_cell_read(cell, NULL));

	nvmem_cell_put(cell);

		if (!IS_ERR(buf)) {

			u8 bin = *((u8 *) buf);

			val = (1 << bin);

			kfree(buf);

		}

		nvmem_cell_put(cell);

	}

	dev_pm_opp_set_supported_hw(dev, &val, 1);

}

/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */

#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/interconnect.h>

#include <linux/pm_domain.h>

#include <linux/pm_opp.h>

static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)

{

	int count, i;

	u64 iova;

	if (IS_ERR_OR_NULL(bo))

		return;

	count = bo->size >> PAGE_SHIFT;

	iova = bo->iova;

	for (i = 0; i < count; i++, iova += PAGE_SIZE) {

		iommu_unmap(gmu->domain, iova, PAGE_SIZE);

		__free_pages(bo->pages[i], 0);

	}

	kfree(bo->pages);

	dma_free_wc(gmu->dev, bo->size, bo->virt, bo->iova);

	kfree(bo);

}

		size_t size)

{

	struct a6xx_gmu_bo *bo;

	int ret, count, i;

	bo = kzalloc(sizeof(*bo), GFP_KERNEL);

	if (!bo)

	bo->size = PAGE_ALIGN(size);

	count = bo->size >> PAGE_SHIFT;

	bo->virt = dma_alloc_wc(gmu->dev, bo->size, &bo->iova, GFP_KERNEL);

	bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);

	if (!bo->pages) {

	if (!bo->virt) {

		kfree(bo);

		return ERR_PTR(-ENOMEM);

	}

	for (i = 0; i < count; i++) {

		bo->pages[i] = alloc_page(GFP_KERNEL);

		if (!bo->pages[i])

			goto err;

	}

	bo->iova = gmu->uncached_iova_base;

	for (i = 0; i < count; i++) {

		ret = iommu_map(gmu->domain,

			bo->iova + (PAGE_SIZE * i),

			page_to_phys(bo->pages[i]), PAGE_SIZE,

			IOMMU_READ | IOMMU_WRITE);

		if (ret) {

			DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer object\n");

			for (i = i - 1 ; i >= 0; i--)

				iommu_unmap(gmu->domain,

					bo->iova + (PAGE_SIZE * i),

					PAGE_SIZE);

			goto err;

		}

	}

	bo->virt = vmap(bo->pages, count, VM_IOREMAP,

		pgprot_writecombine(PAGE_KERNEL));

	if (!bo->virt)

		goto err;

	/* Align future IOVA addresses on 1MB boundaries */

	gmu->uncached_iova_base += ALIGN(size, SZ_1M);

	return bo;

err:

	for (i = 0; i < count; i++) {

		if (bo->pages[i])

			__free_pages(bo->pages[i], 0);

	}

	kfree(bo->pages);

	kfree(bo);

	return ERR_PTR(-ENOMEM);

}

static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)

{

	int ret;

	/*

	 * The GMU address space is hardcoded to treat the range

	 * 0x60000000 - 0x80000000 as un-cached memory. All buffers shared

	 * between the GMU and the CPU will live in this space

	 */

	gmu->uncached_iova_base = 0x60000000;

	gmu->domain = iommu_domain_alloc(&platform_bus_type);

	if (!gmu->domain)

		return -ENODEV;

	ret = iommu_attach_device(gmu->domain, gmu->dev);

	if (ret) {

		iommu_domain_free(gmu->domain);

		gmu->domain = NULL;

	}

	return ret;

}

/* Return the 'arc-level' for the given frequency */

	a6xx_gmu_memory_free(gmu, gmu->hfi);

	iommu_detach_device(gmu->domain, gmu->dev);

	iommu_domain_free(gmu->domain);

	free_irq(gmu->gmu_irq, gmu);

	free_irq(gmu->hfi_irq, gmu);

	gmu->dev = &pdev->dev;

	of_dma_configure(gmu->dev, node, true);

	/* Pass force_dma false to require the DT to set the dma region */

	ret = of_dma_configure(gmu->dev, node, false);

	if (ret)

		return ret;

	/* Set the mask after the of_dma_configure() */

	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(31));

	if (ret)

		return ret;

	/* Fow now, don't do anything fancy until we get our feet under us */

	gmu->idle_level = GMU_IDLE_STATE_ACTIVE;

	if (ret)

		goto err_put_device;

	/* Set up the IOMMU context bank */

	ret = a6xx_gmu_memory_probe(gmu);

	if (ret)

		goto err_put_device;

	/* Allocate memory for for the HFI queues */

	gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K);

	if (IS_ERR(gmu->hfi))

err_memory:

	a6xx_gmu_memory_free(gmu, gmu->hfi);

	if (gmu->domain) {

		iommu_detach_device(gmu->domain, gmu->dev);

		iommu_domain_free(gmu->domain);

	}

	ret = -ENODEV;

err_put_device: