drm/amd/display: work around fp code being emitted outside of DC_FP_START/END

	return out;

}

bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

		bool fast_validate)

/*

 * This must be noinline to ensure anything that deals with FP registers

 * is contained within this call; previously our compiling with hard-float

 * would result in fp instructions being emitted outside of the boundaries

 * of the DC_FP_START/END macros, which makes sense as the compiler has no

 * idea about what is wrapped and what is not

 *

 * This is largely just a workaround to avoid breakage introduced with 5.6,

 * ideally all fp-using code should be moved into its own file, only that

 * should be compiled with hard-float, and all code exported from there

 * should be strictly wrapped with DC_FP_START/END

 */

static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,

		struct dc_state *context, bool fast_validate)

{

	bool voltage_supported = false;

	bool full_pstate_supported = false;

	bool dummy_pstate_supported = false;

	double p_state_latency_us;

	DC_FP_START();

	p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =

		dc->debug.disable_dram_clock_change_vactive_support;

	if (fast_validate) {

		voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);

		DC_FP_END();

		return voltage_supported;

		return dcn20_validate_bandwidth_internal(dc, context, true);

	}

	// Best case, we support full UCLK switch latency

restore_dml_state:

	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;

	return voltage_supported;

}

bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

		bool fast_validate)

{

	bool voltage_supported = false;

	DC_FP_START();

	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);

	DC_FP_END();

	return voltage_supported;

}