Commit 59c14e5e authored by Wojciech Ziemba's avatar Wojciech Ziemba Committed by Herbert Xu
Browse files

crypto: qat - replace user types with kernel ABI __u types 



Kernel source code should not contain stdint.h types.
This patch replaces uintXX_t types with kernel space ABI types.

Signed-off-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 2bfd2276

drivers/crypto/qat/qat_common/adf_cfg_common.h

+12 −12
Original line number Diff line number Diff line
@@ -37,16 +37,16 @@ enum adf_device_type { 


struct adf_dev_status_info {

	enum adf_device_type type;

	u32 accel_id;

	u32 instance_id;

	uint8_t num_ae;

	uint8_t num_accel;

	uint8_t num_logical_accel;

	uint8_t banks_per_accel;

	uint8_t state;

	uint8_t bus;

	uint8_t dev;

	uint8_t fun;

	__u32 accel_id;

	__u32 instance_id;

	__u8 num_ae;

	__u8 num_accel;

	__u8 num_logical_accel;

	__u8 banks_per_accel;

	__u8 state;

	__u8 bus;

	__u8 dev;

	__u8 fun;

	char name[MAX_DEVICE_NAME_SIZE];

};
@@ -57,6 +57,6 @@ struct adf_dev_status_info { 
		struct adf_user_cfg_ctl_data)

#define IOCTL_START_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 2, \

		struct adf_user_cfg_ctl_data)

#define IOCTL_STATUS_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 3, uint32_t)

#define IOCTL_GET_NUM_DEVICES _IOW(ADF_CTL_IOC_MAGIC, 4, int32_t)

#define IOCTL_STATUS_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 3, __u32)

#define IOCTL_GET_NUM_DEVICES _IOW(ADF_CTL_IOC_MAGIC, 4, __s32)

#endif

drivers/crypto/qat/qat_common/adf_cfg_user.h

+5 −5
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ struct adf_user_cfg_key_val { 
	char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES];

	union {

		struct adf_user_cfg_key_val *next;

		uint64_t padding3;

		__u64 padding3;

	};

	enum adf_cfg_val_type type;

} __packed;
@@ -20,19 +20,19 @@ struct adf_user_cfg_section { 
	char name[ADF_CFG_MAX_SECTION_LEN_IN_BYTES];

	union {

		struct adf_user_cfg_key_val *params;

		uint64_t padding1;

		__u64 padding1;

	};

	union {

		struct adf_user_cfg_section *next;

		uint64_t padding3;

		__u64 padding3;

	};

} __packed;



struct adf_user_cfg_ctl_data {

	union {

		struct adf_user_cfg_section *config_section;

		uint64_t padding;

		__u64 padding;

	};

	uint8_t device_id;

	__u8 device_id;

} __packed;

#endif

drivers/crypto/qat/qat_common/icp_qat_fw.h

+29 −29
Original line number Diff line number Diff line
@@ -45,41 +45,41 @@ enum icp_qat_fw_comn_request_id { 
struct icp_qat_fw_comn_req_hdr_cd_pars {

	union {

		struct {

			uint64_t content_desc_addr;

			uint16_t content_desc_resrvd1;

			uint8_t content_desc_params_sz;

			uint8_t content_desc_hdr_resrvd2;

			uint32_t content_desc_resrvd3;

			__u64 content_desc_addr;

			__u16 content_desc_resrvd1;

			__u8 content_desc_params_sz;

			__u8 content_desc_hdr_resrvd2;

			__u32 content_desc_resrvd3;

		} s;

		struct {

			uint32_t serv_specif_fields[4];

			__u32 serv_specif_fields[4];

		} s1;

	} u;

};



struct icp_qat_fw_comn_req_mid {

	uint64_t opaque_data;

	uint64_t src_data_addr;

	uint64_t dest_data_addr;

	uint32_t src_length;

	uint32_t dst_length;

	__u64 opaque_data;

	__u64 src_data_addr;

	__u64 dest_data_addr;

	__u32 src_length;

	__u32 dst_length;

};



struct icp_qat_fw_comn_req_cd_ctrl {

	uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];

	__u32 content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];

};



struct icp_qat_fw_comn_req_hdr {

	uint8_t resrvd1;

	uint8_t service_cmd_id;

	uint8_t service_type;

	uint8_t hdr_flags;

	uint16_t serv_specif_flags;

	uint16_t comn_req_flags;

	__u8 resrvd1;

	__u8 service_cmd_id;

	__u8 service_type;

	__u8 hdr_flags;

	__u16 serv_specif_flags;

	__u16 comn_req_flags;

};



struct icp_qat_fw_comn_req_rqpars {

	uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];

	__u32 serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];

};



struct icp_qat_fw_comn_req {
@@ -91,24 +91,24 @@ struct icp_qat_fw_comn_req { 
};



struct icp_qat_fw_comn_error {

	uint8_t xlat_err_code;

	uint8_t cmp_err_code;

	__u8 xlat_err_code;

	__u8 cmp_err_code;

};



struct icp_qat_fw_comn_resp_hdr {

	uint8_t resrvd1;

	uint8_t service_id;

	uint8_t response_type;

	uint8_t hdr_flags;

	__u8 resrvd1;

	__u8 service_id;

	__u8 response_type;

	__u8 hdr_flags;

	struct icp_qat_fw_comn_error comn_error;

	uint8_t comn_status;

	uint8_t cmd_id;

	__u8 comn_status;

	__u8 cmd_id;

};



struct icp_qat_fw_comn_resp {

	struct icp_qat_fw_comn_resp_hdr comn_hdr;

	uint64_t opaque_data;

	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];

	__u64 opaque_data;

	__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];

};



#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1

drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h

+23 −23
Original line number Diff line number Diff line
@@ -23,35 +23,35 @@ enum icp_qat_fw_init_admin_resp_status { 
};



struct icp_qat_fw_init_admin_req {

	uint16_t init_cfg_sz;

	uint8_t resrvd1;

	uint8_t init_admin_cmd_id;

	uint32_t resrvd2;

	uint64_t opaque_data;

	uint64_t init_cfg_ptr;

	uint64_t resrvd3;

	__u16 init_cfg_sz;

	__u8 resrvd1;

	__u8 init_admin_cmd_id;

	__u32 resrvd2;

	__u64 opaque_data;

	__u64 init_cfg_ptr;

	__u64 resrvd3;

};



struct icp_qat_fw_init_admin_resp_hdr {

	uint8_t flags;

	uint8_t resrvd1;

	uint8_t status;

	uint8_t init_admin_cmd_id;

	__u8 flags;

	__u8 resrvd1;

	__u8 status;

	__u8 init_admin_cmd_id;

};



struct icp_qat_fw_init_admin_resp_pars {

	union {

		uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_4];

		__u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_4];

		struct {

			uint32_t version_patch_num;

			uint8_t context_id;

			uint8_t ae_id;

			uint16_t resrvd1;

			uint64_t resrvd2;

			__u32 version_patch_num;

			__u8 context_id;

			__u8 ae_id;

			__u16 resrvd1;

			__u64 resrvd2;

		} s1;

		struct {

			uint64_t req_rec_count;

			uint64_t resp_sent_count;

			__u64 req_rec_count;

			__u64 resp_sent_count;

		} s2;

	} u;

};
@@ -59,13 +59,13 @@ struct icp_qat_fw_init_admin_resp_pars { 
struct icp_qat_fw_init_admin_resp {

	struct icp_qat_fw_init_admin_resp_hdr init_resp_hdr;

	union {

		uint32_t resrvd2;

		__u32 resrvd2;

		struct {

			uint16_t version_minor_num;

			uint16_t version_major_num;

			__u16 version_minor_num;

			__u16 version_major_num;

		} s;

	} u;

	uint64_t opaque_data;

	__u64 opaque_data;

	struct icp_qat_fw_init_admin_resp_pars init_resp_pars;

};

drivers/crypto/qat/qat_common/icp_qat_fw_la.h

+79 −79
Original line number Diff line number Diff line
@@ -182,14 +182,14 @@ struct icp_qat_fw_la_bulk_req { 
struct icp_qat_fw_cipher_req_hdr_cd_pars {

	union {

		struct {

			uint64_t content_desc_addr;

			uint16_t content_desc_resrvd1;

			uint8_t content_desc_params_sz;

			uint8_t content_desc_hdr_resrvd2;

			uint32_t content_desc_resrvd3;

			__u64 content_desc_addr;

			__u16 content_desc_resrvd1;

			__u8 content_desc_params_sz;

			__u8 content_desc_hdr_resrvd2;

			__u32 content_desc_resrvd3;

		} s;

		struct {

			uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];

			__u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];

		} s1;

	} u;

};
@@ -197,70 +197,70 @@ struct icp_qat_fw_cipher_req_hdr_cd_pars { 
struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {

	union {

		struct {

			uint64_t content_desc_addr;

			uint16_t content_desc_resrvd1;

			uint8_t content_desc_params_sz;

			uint8_t content_desc_hdr_resrvd2;

			uint32_t content_desc_resrvd3;

			__u64 content_desc_addr;

			__u16 content_desc_resrvd1;

			__u8 content_desc_params_sz;

			__u8 content_desc_hdr_resrvd2;

			__u32 content_desc_resrvd3;

		} s;

		struct {

			uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];

			__u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];

		} sl;

	} u;

};



struct icp_qat_fw_cipher_cd_ctrl_hdr {

	uint8_t cipher_state_sz;

	uint8_t cipher_key_sz;

	uint8_t cipher_cfg_offset;

	uint8_t next_curr_id;

	uint8_t cipher_padding_sz;

	uint8_t resrvd1;

	uint16_t resrvd2;

	uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];

	__u8 cipher_state_sz;

	__u8 cipher_key_sz;

	__u8 cipher_cfg_offset;

	__u8 next_curr_id;

	__u8 cipher_padding_sz;

	__u8 resrvd1;

	__u16 resrvd2;

	__u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];

};



struct icp_qat_fw_auth_cd_ctrl_hdr {

	uint32_t resrvd1;

	uint8_t resrvd2;

	uint8_t hash_flags;

	uint8_t hash_cfg_offset;

	uint8_t next_curr_id;

	uint8_t resrvd3;

	uint8_t outer_prefix_sz;

	uint8_t final_sz;

	uint8_t inner_res_sz;

	uint8_t resrvd4;

	uint8_t inner_state1_sz;

	uint8_t inner_state2_offset;

	uint8_t inner_state2_sz;

	uint8_t outer_config_offset;

	uint8_t outer_state1_sz;

	uint8_t outer_res_sz;

	uint8_t outer_prefix_offset;

	__u32 resrvd1;

	__u8 resrvd2;

	__u8 hash_flags;

	__u8 hash_cfg_offset;

	__u8 next_curr_id;

	__u8 resrvd3;

	__u8 outer_prefix_sz;

	__u8 final_sz;

	__u8 inner_res_sz;

	__u8 resrvd4;

	__u8 inner_state1_sz;

	__u8 inner_state2_offset;

	__u8 inner_state2_sz;

	__u8 outer_config_offset;

	__u8 outer_state1_sz;

	__u8 outer_res_sz;

	__u8 outer_prefix_offset;

};



struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {

	uint8_t cipher_state_sz;

	uint8_t cipher_key_sz;

	uint8_t cipher_cfg_offset;

	uint8_t next_curr_id_cipher;

	uint8_t cipher_padding_sz;

	uint8_t hash_flags;

	uint8_t hash_cfg_offset;

	uint8_t next_curr_id_auth;

	uint8_t resrvd1;

	uint8_t outer_prefix_sz;

	uint8_t final_sz;

	uint8_t inner_res_sz;

	uint8_t resrvd2;

	uint8_t inner_state1_sz;

	uint8_t inner_state2_offset;

	uint8_t inner_state2_sz;

	uint8_t outer_config_offset;

	uint8_t outer_state1_sz;

	uint8_t outer_res_sz;

	uint8_t outer_prefix_offset;

	__u8 cipher_state_sz;

	__u8 cipher_key_sz;

	__u8 cipher_cfg_offset;

	__u8 next_curr_id_cipher;

	__u8 cipher_padding_sz;

	__u8 hash_flags;

	__u8 hash_cfg_offset;

	__u8 next_curr_id_auth;

	__u8 resrvd1;

	__u8 outer_prefix_sz;

	__u8 final_sz;

	__u8 inner_res_sz;

	__u8 resrvd2;

	__u8 inner_state1_sz;

	__u8 inner_state2_offset;

	__u8 inner_state2_sz;

	__u8 outer_config_offset;

	__u8 outer_state1_sz;

	__u8 outer_res_sz;

	__u8 outer_prefix_offset;

};



#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
@@ -271,48 +271,48 @@ struct icp_qat_fw_cipher_auth_cd_ctrl_hdr { 
#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)



struct icp_qat_fw_la_cipher_req_params {

	uint32_t cipher_offset;

	uint32_t cipher_length;

	__u32 cipher_offset;

	__u32 cipher_length;

	union {

		uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];

		__u32 cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];

		struct {

			uint64_t cipher_IV_ptr;

			uint64_t resrvd1;

			__u64 cipher_IV_ptr;

			__u64 resrvd1;

		} s;

	} u;

};



struct icp_qat_fw_la_auth_req_params {

	uint32_t auth_off;

	uint32_t auth_len;

	__u32 auth_off;

	__u32 auth_len;

	union {

		uint64_t auth_partial_st_prefix;

		uint64_t aad_adr;

		__u64 auth_partial_st_prefix;

		__u64 aad_adr;

	} u1;

	uint64_t auth_res_addr;

	__u64 auth_res_addr;

	union {

		uint8_t inner_prefix_sz;

		uint8_t aad_sz;

		__u8 inner_prefix_sz;

		__u8 aad_sz;

	} u2;

	uint8_t resrvd1;

	uint8_t hash_state_sz;

	uint8_t auth_res_sz;

	__u8 resrvd1;

	__u8 hash_state_sz;

	__u8 auth_res_sz;

} __packed;



struct icp_qat_fw_la_auth_req_params_resrvd_flds {

	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];

	__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];

	union {

		uint8_t inner_prefix_sz;

		uint8_t aad_sz;

		__u8 inner_prefix_sz;

		__u8 aad_sz;

	} u2;

	uint8_t resrvd1;

	uint16_t resrvd2;

	__u8 resrvd1;

	__u16 resrvd2;

};



struct icp_qat_fw_la_resp {

	struct icp_qat_fw_comn_resp_hdr comn_resp;

	uint64_t opaque_data;

	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];

	__u64 opaque_data;

	__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];

};



#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \

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