ARM: dts: dra7-evm: Fix NAND GPMC timings (5990047c) · Commits · 戴 / test

The nand timings were scaled down by 2 to account for the 2x rate returned by clk_get_rate(gpmc_fclk). As the clock data got fixed by [1], revert back to actual timings (i.e. scale them up by 2). Without this NAND doesn't work on dra7-evm. [1] - commit ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates Fixes: ("ARM: dts: dra7: add support for parallel NAND flash") Cc: <stable@vger.kernel.org> [3.16] Signed-off-by:

Roger Quadros <rogerq@ti.com> Signed-off-by:

Tony Lindgren <tony@atomide.com>

arch/arm/boot/dts/dra7-evm.dts

+12 −15

Original line number	Diff line number	Diff line
		@@ -447,22 +447,19 @@
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <40>;
		gpmc,cs-wr-off-ns = <40>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <30>;
		gpmc,adv-wr-off-ns = <30>;
		gpmc,we-on-ns = <5>;
		gpmc,we-off-ns = <25>;
		gpmc,oe-on-ns = <2>;
		gpmc,oe-off-ns = <20>;
		gpmc,access-ns = <20>;
		gpmc,wr-access-ns = <40>;
		gpmc,rd-cycle-ns = <40>;
		gpmc,wr-cycle-ns = <40>;
		gpmc,wait-pin = <0>;
		gpmc,wait-on-read;
		gpmc,wait-on-write;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;

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