powerpc/e6500: Add architecture categories for e6500 cores

===================================================================

Power Architecture CPU Binding

Copyright 2013 Freescale Semiconductor Inc.

Power Architecture CPUs in Freescale SOCs are represented in device trees as

per the definition in ePAPR.

In addition to the ePAPR definitions, the properties defined below may be

present on CPU nodes.

PROPERTIES

   - fsl,eref-*

        Usage: optional

        Value type: <empty>

        Definition: The EREF (EREF: A Programmer.s Reference Manual for

	Freescale Power Architecture) defines the architecture for Freescale

	Power CPUs.  The EREF defines some architecture categories not defined

	by the Power ISA.  For these EREF-specific categories, the existence of

	a property named fsl,eref-[CAT], where [CAT] is the abbreviated category

	name with all uppercase letters converted to lowercase, indicates that

	the category is supported by the implementation.

/*

 * e6500 Power ISA Device Tree Source (include)

 *

 * Copyright 2013 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

/ {

	cpus {

		power-isa-version = "2.06";

		power-isa-b;		// Base

		power-isa-e;		// Embedded

		power-isa-atb;		// Alternate Time Base

		power-isa-cs;		// Cache Specification

		power-isa-ds;		// Decorated Storage

		power-isa-e.ed;		// Embedded.Enhanced Debug

		power-isa-e.pd;		// Embedded.External PID

		power-isa-e.hv;		// Embedded.Hypervisor

		power-isa-e.le;		// Embedded.Little-Endian

		power-isa-e.pm;		// Embedded.Performance Monitor

		power-isa-e.pc;		// Embedded.Processor Control

		power-isa-ecl;		// Embedded Cache Locking

		power-isa-exp;		// External Proxy

		power-isa-fp;		// Floating Point

		power-isa-fp.r;		// Floating Point.Record

		power-isa-mmc;		// Memory Coherence

		power-isa-scpm;		// Store Conditional Page Mobility

		power-isa-wt;		// Wait

		power-isa-64;		// 64-bit

		power-isa-e.pt;		// Embedded.Page Table

		power-isa-e.hv.lrat;	// Embedded.Hypervisor.LRAT

		power-isa-e.em;		// Embedded Multi-Threading

		power-isa-v;		// Vector (AltiVec)

		fsl,eref-er;		// Enhanced Reservations (Load and Reserve and Store Cond.)

		fsl,eref-deo;		// Data Cache Extended Operations

		mmu-type = "power-embedded";

	};

};