Commit 59815d6d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC fixes from Ulf Hansson:

 - Fix HS400 tuning for ACPI ID AMDI0040

 - Fix reset of CQHCI for Intel GLK-based controllers

 - Use correct timeout clock for Tegra186/194/210

 - Fix eMMC mounting on mt7622/Bpi-64

* tag 'mmc-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  sdhci: tegra: Add missing TMCLK for data timeout
  arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodes
  arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes
  arm64: tegra: Add missing timeout clock to Tegra210 SDMMC
  dt-bindings: mmc: tegra: Add tmclk for Tegra210 and later
  sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra186
  sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra210
  arm64: dts: mt7622: add reset node for mmc device
  dt-bindings: mmc: Add missing description for clk_in/out_sd1
  mmc: mediatek: add optional module reset property
  mmc: dt-bindings: Add resets/reset-names for Mediatek MMC bindings
  mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers
  mmc: sdhci-acpi: Fix HS400 tuning for AMDI0040
parents f75aef39 8048822b

Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml

+7 −3
Original line number Diff line number Diff line
@@ -30,9 +30,13 @@ allOf: 
    then:

      properties:

        clock-output-names:

          items:

          oneOf:

            - items:

              - const: clk_out_sd0

              - const: clk_in_sd0

            - items:

              - const: clk_out_sd1

              - const: clk_in_sd1



properties:

  compatible:

Documentation/devicetree/bindings/mmc/mtk-sd.txt

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ Optional properties: 
		     error caused by stop clock(fifo full)

		     Valid range = [0:0x7]. if not present, default value is 0.

		     applied to compatible "mediatek,mt2701-mmc".

- resets: Phandle and reset specifier pair to softreset line of MSDC IP.

- reset-names: Should be "hrst".



Examples:

mmc0: mmc@11230000 {

Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt

+29 −3
Original line number Diff line number Diff line
@@ -15,8 +15,15 @@ Required properties: 
  - "nvidia,tegra210-sdhci": for Tegra210

  - "nvidia,tegra186-sdhci": for Tegra186

  - "nvidia,tegra194-sdhci": for Tegra194

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.

- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.

	  One for the module clock and one for the timeout clock.

	  For all other Tegra devices, must contain a single entry for

	  the module clock. See ../clocks/clock-bindings.txt for details.

- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the

	       strings 'sdhci' and 'tmclk' to represent the module and

	       the timeout clocks, respectively.

	       For all other Tegra devices must contain the string 'sdhci'

	       to represent the module clock.

- resets : Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names : Must include the following entries:
@@ -99,7 +106,7 @@ Optional properties for Tegra210, Tegra186 and Tegra194: 


Example:

sdhci@700b0000 {

	compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";

	compatible = "nvidia,tegra124-sdhci";

	reg = <0x0 0x700b0000 0x0 0x200>;

	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
@@ -115,3 +122,22 @@ sdhci@700b0000 { 
	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;

	status = "disabled";

};



sdhci@700b0000 {

	compatible = "nvidia,tegra210-sdhci";

	reg = <0x0 0x700b0000 0x0 0x200>;

	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,

		 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;

	clock-names = "sdhci", "tmclk";

	resets = <&tegra_car 14>;

	reset-names = "sdhci";

	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";

	pinctrl-0 = <&sdmmc1_3v3>;

	pinctrl-1 = <&sdmmc1_1v8>;

	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;

	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;

	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;

	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;

	status = "disabled";

};

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -686,6 +686,8 @@ 
		clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,

			 <&topckgen CLK_TOP_MSDC50_0_SEL>;

		clock-names = "source", "hclk";

		resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;

		reset-names = "hrst";

		status = "disabled";

	};

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+12 −8
Original line number Diff line number Diff line
@@ -337,8 +337,9 @@ 
		compatible = "nvidia,tegra186-sdhci";

		reg = <0x0 0x03400000 0x0 0x10000>;

		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&bpmp TEGRA186_CLK_SDMMC1>;

		clock-names = "sdhci";

		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,

			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;

		clock-names = "sdhci", "tmclk";

		resets = <&bpmp TEGRA186_RESET_SDMMC1>;

		reset-names = "sdhci";

		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -366,8 +367,9 @@ 
		compatible = "nvidia,tegra186-sdhci";

		reg = <0x0 0x03420000 0x0 0x10000>;

		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&bpmp TEGRA186_CLK_SDMMC2>;

		clock-names = "sdhci";

		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,

			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;

		clock-names = "sdhci", "tmclk";

		resets = <&bpmp TEGRA186_RESET_SDMMC2>;

		reset-names = "sdhci";

		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
@@ -390,8 +392,9 @@ 
		compatible = "nvidia,tegra186-sdhci";

		reg = <0x0 0x03440000 0x0 0x10000>;

		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&bpmp TEGRA186_CLK_SDMMC3>;

		clock-names = "sdhci";

		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,

			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;

		clock-names = "sdhci", "tmclk";

		resets = <&bpmp TEGRA186_RESET_SDMMC3>;

		reset-names = "sdhci";

		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
@@ -416,8 +419,9 @@ 
		compatible = "nvidia,tegra186-sdhci";

		reg = <0x0 0x03460000 0x0 0x10000>;

		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&bpmp TEGRA186_CLK_SDMMC4>;

		clock-names = "sdhci";

		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,

			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;

		clock-names = "sdhci", "tmclk";

		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,

				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;

		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;

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