drm/i915/display: move clk off sanitize to its own function (5956f440) · Commits · 戴 / test

drivers/gpu/drm/i915/display/intel_ddi.c

+32 −25

Original line number	Diff line number	Diff line
		@@ -2999,11 +2999,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
		mutex_unlock(&dev_priv->dpll_lock);
		}

		static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
		u32 port_mask, bool ddi_clk_needed)
		{
		enum port port;
		u32 val;

		val = I915_READ(ICL_DPCLKA_CFGCR0);
		for_each_port_masked(port, port_mask) {
		enum phy phy = intel_port_to_phy(dev_priv, port);

		bool ddi_clk_ungated = !(val &
		icl_dpclka_cfgcr0_clk_off(dev_priv,
		phy));

		if (ddi_clk_needed == ddi_clk_ungated)
		continue;

		/*
		* Punt on the case now where clock is gated, but it would
		* be needed by the port. Something else is really broken then.
		*/
		if (WARN_ON(ddi_clk_needed))
		continue;

		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
		phy_name(port));
		val \|= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
		}
		}

		void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
		{
		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		u32 val;
		enum port port;
		u32 port_mask;
		bool ddi_clk_needed;

		@@ -3052,29 +3081,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
		ddi_clk_needed = false;
		}

		val = I915_READ(ICL_DPCLKA_CFGCR0);
		for_each_port_masked(port, port_mask) {
		enum phy phy = intel_port_to_phy(dev_priv, port);

		bool ddi_clk_ungated = !(val &
		icl_dpclka_cfgcr0_clk_off(dev_priv,
		phy));

		if (ddi_clk_needed == ddi_clk_ungated)
		continue;

		/*
		* Punt on the case now where clock is gated, but it would
		* be needed by the port. Something else is really broken then.
		*/
		if (WARN_ON(ddi_clk_needed))
		continue;

		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
		phy_name(port));
		val \|= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
		}
		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
		}

		static void intel_ddi_clk_select(struct intel_encoder *encoder,

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