Commit 59534f72 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (207 commits)
  drm/radeon/kms/pm/r600: select the mid clock mode for single head low profile
  drm/radeon: fix power supply kconfig interaction.
  drm/radeon/kms: record object that have been list reserved
  drm/radeon: AGP memory is only I/O if the aperture can be mapped by the CPU.
  drm/radeon/kms: don't default display priority to high on rs4xx
  drm/edid: fix typo in 1600x1200@75 mode
  drm/nouveau: fix i2c-related init table handlers
  drm/nouveau: support init table i2c device identifier 0x81
  drm/nouveau: ensure we've parsed i2c table entry for INIT_*I2C* handlers
  drm/nouveau: display error message for any failed init table opcode
  drm/nouveau: fix init table handlers to return proper error codes
  drm/nv50: support fractional feedback divider on newer chips
  drm/nv50: fix monitor detection on certain chipsets
  drm/nv50: store full dcb i2c entry from vbios
  drm/nv50: fix suspend/resume with DP outputs
  drm/nv50: output calculated crtc pll when debugging on
  drm/nouveau: dump pll limits entries when debugging is on
  drm/nouveau: bios parser fixes for eDP boards
  drm/nouveau: fix a nouveau_bo dereference after it's been destroyed
  drm/nv40: remove some completed ctxprog TODOs
  ...
parents ac3ee84c b486787e

Documentation/DocBook/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ DOCBOOKS := z8530book.xml mcabook.xml device-drivers.xml \ 
	    genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \

	    mac80211.xml debugobjects.xml sh.xml regulator.xml \

	    alsa-driver-api.xml writing-an-alsa-driver.xml \

	    tracepoint.xml media.xml

	    tracepoint.xml media.xml drm.xml



###

# The build process is as follows (targets):

Documentation/DocBook/drm.tmpl

0 → 100644
+839 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/x86/include/asm/cacheflush.h

+2 −0
Original line number Diff line number Diff line
@@ -145,9 +145,11 @@ int set_memory_np(unsigned long addr, int numpages); 
int set_memory_4k(unsigned long addr, int numpages);



int set_memory_array_uc(unsigned long *addr, int addrinarray);

int set_memory_array_wc(unsigned long *addr, int addrinarray);

int set_memory_array_wb(unsigned long *addr, int addrinarray);



int set_pages_array_uc(struct page **pages, int addrinarray);

int set_pages_array_wc(struct page **pages, int addrinarray);

int set_pages_array_wb(struct page **pages, int addrinarray);



/*

arch/x86/mm/pageattr.c

+45 −8
Original line number Diff line number Diff line
@@ -997,7 +997,8 @@ out_err: 
}

EXPORT_SYMBOL(set_memory_uc);



int set_memory_array_uc(unsigned long *addr, int addrinarray)

int _set_memory_array(unsigned long *addr, int addrinarray,

		unsigned long new_type)

{

	int i, j;

	int ret;
@@ -1007,13 +1008,19 @@ int set_memory_array_uc(unsigned long *addr, int addrinarray) 
	 */

	for (i = 0; i < addrinarray; i++) {

		ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,

					_PAGE_CACHE_UC_MINUS, NULL);

					new_type, NULL);

		if (ret)

			goto out_free;

	}



	ret = change_page_attr_set(addr, addrinarray,

				    __pgprot(_PAGE_CACHE_UC_MINUS), 1);



	if (!ret && new_type == _PAGE_CACHE_WC)

		ret = change_page_attr_set_clr(addr, addrinarray,

					       __pgprot(_PAGE_CACHE_WC),

					       __pgprot(_PAGE_CACHE_MASK),

					       0, CPA_ARRAY, NULL);

	if (ret)

		goto out_free;
@@ -1025,8 +1032,19 @@ out_free: 


	return ret;

}



int set_memory_array_uc(unsigned long *addr, int addrinarray)

{

	return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);

}

EXPORT_SYMBOL(set_memory_array_uc);



int set_memory_array_wc(unsigned long *addr, int addrinarray)

{

	return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);

}

EXPORT_SYMBOL(set_memory_array_wc);



int _set_memory_wc(unsigned long addr, int numpages)

{

	int ret;
@@ -1153,26 +1171,34 @@ int set_pages_uc(struct page *page, int numpages) 
}

EXPORT_SYMBOL(set_pages_uc);



int set_pages_array_uc(struct page **pages, int addrinarray)

static int _set_pages_array(struct page **pages, int addrinarray,

		unsigned long new_type)

{

	unsigned long start;

	unsigned long end;

	int i;

	int free_idx;

	int ret;



	for (i = 0; i < addrinarray; i++) {

		if (PageHighMem(pages[i]))

			continue;

		start = page_to_pfn(pages[i]) << PAGE_SHIFT;

		end = start + PAGE_SIZE;

		if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))

		if (reserve_memtype(start, end, new_type, NULL))

			goto err_out;

	}



	if (cpa_set_pages_array(pages, addrinarray,

			__pgprot(_PAGE_CACHE_UC_MINUS)) == 0) {

	ret = cpa_set_pages_array(pages, addrinarray,

			__pgprot(_PAGE_CACHE_UC_MINUS));

	if (!ret && new_type == _PAGE_CACHE_WC)

		ret = change_page_attr_set_clr(NULL, addrinarray,

					       __pgprot(_PAGE_CACHE_WC),

					       __pgprot(_PAGE_CACHE_MASK),

					       0, CPA_PAGES_ARRAY, pages);

	if (ret)

		goto err_out;

	return 0; /* Success */

	}

err_out:

	free_idx = i;

	for (i = 0; i < free_idx; i++) {
@@ -1184,8 +1210,19 @@ err_out: 
	}

	return -EINVAL;

}



int set_pages_array_uc(struct page **pages, int addrinarray)

{

	return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);

}

EXPORT_SYMBOL(set_pages_array_uc);



int set_pages_array_wc(struct page **pages, int addrinarray)

{

	return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);

}

EXPORT_SYMBOL(set_pages_array_wc);



int set_pages_wb(struct page *page, int numpages)

{

	unsigned long addr = (unsigned long)page_address(page);

drivers/char/agp/agp.h

+0 −80
Original line number Diff line number Diff line
@@ -178,86 +178,6 @@ struct agp_bridge_data { 
#define PGE_EMPTY(b, p)	(!(p) || (p) == (unsigned long) (b)->scratch_page)





/* Intel registers */

#define INTEL_APSIZE	0xb4

#define INTEL_ATTBASE	0xb8

#define INTEL_AGPCTRL	0xb0

#define INTEL_NBXCFG	0x50

#define INTEL_ERRSTS	0x91



/* Intel i830 registers */

#define I830_GMCH_CTRL			0x52

#define I830_GMCH_ENABLED		0x4

#define I830_GMCH_MEM_MASK		0x1

#define I830_GMCH_MEM_64M		0x1

#define I830_GMCH_MEM_128M		0

#define I830_GMCH_GMS_MASK		0x70

#define I830_GMCH_GMS_DISABLED		0x00

#define I830_GMCH_GMS_LOCAL		0x10

#define I830_GMCH_GMS_STOLEN_512	0x20

#define I830_GMCH_GMS_STOLEN_1024	0x30

#define I830_GMCH_GMS_STOLEN_8192	0x40

#define I830_RDRAM_CHANNEL_TYPE		0x03010

#define I830_RDRAM_ND(x)		(((x) & 0x20) >> 5)

#define I830_RDRAM_DDT(x)		(((x) & 0x18) >> 3)



/* This one is for I830MP w. an external graphic card */

#define INTEL_I830_ERRSTS	0x92



/* Intel 855GM/852GM registers */

#define I855_GMCH_GMS_MASK		0xF0

#define I855_GMCH_GMS_STOLEN_0M		0x0

#define I855_GMCH_GMS_STOLEN_1M		(0x1 << 4)

#define I855_GMCH_GMS_STOLEN_4M		(0x2 << 4)

#define I855_GMCH_GMS_STOLEN_8M		(0x3 << 4)

#define I855_GMCH_GMS_STOLEN_16M	(0x4 << 4)

#define I855_GMCH_GMS_STOLEN_32M	(0x5 << 4)

#define I85X_CAPID			0x44

#define I85X_VARIANT_MASK		0x7

#define I85X_VARIANT_SHIFT		5

#define I855_GME			0x0

#define I855_GM				0x4

#define I852_GME			0x2

#define I852_GM				0x5



/* Intel i845 registers */

#define INTEL_I845_AGPM		0x51

#define INTEL_I845_ERRSTS	0xc8



/* Intel i860 registers */

#define INTEL_I860_MCHCFG	0x50

#define INTEL_I860_ERRSTS	0xc8



/* Intel i810 registers */

#define I810_GMADDR		0x10

#define I810_MMADDR		0x14

#define I810_PTE_BASE		0x10000

#define I810_PTE_MAIN_UNCACHED	0x00000000

#define I810_PTE_LOCAL		0x00000002

#define I810_PTE_VALID		0x00000001

#define I830_PTE_SYSTEM_CACHED  0x00000006

#define I810_SMRAM_MISCC	0x70

#define I810_GFX_MEM_WIN_SIZE	0x00010000

#define I810_GFX_MEM_WIN_32M	0x00010000

#define I810_GMS		0x000000c0

#define I810_GMS_DISABLE	0x00000000

#define I810_PGETBL_CTL		0x2020

#define I810_PGETBL_ENABLED	0x00000001

#define I965_PGETBL_SIZE_MASK	0x0000000e

#define I965_PGETBL_SIZE_512KB	(0 << 1)

#define I965_PGETBL_SIZE_256KB	(1 << 1)

#define I965_PGETBL_SIZE_128KB	(2 << 1)

#define I965_PGETBL_SIZE_1MB	(3 << 1)

#define I965_PGETBL_SIZE_2MB	(4 << 1)

#define I965_PGETBL_SIZE_1_5MB	(5 << 1)

#define G33_PGETBL_SIZE_MASK    (3 << 8)

#define G33_PGETBL_SIZE_1M      (1 << 8)

#define G33_PGETBL_SIZE_2M      (2 << 8)



#define I810_DRAM_CTL		0x3000

#define I810_DRAM_ROW_0		0x00000001

#define I810_DRAM_ROW_0_SDRAM	0x00000001



struct agp_device_ids {

	unsigned short device_id; /* first, to make table easier to read */

	enum chipset_type chipset;

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