Commit 5947a64a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The interrupt brigade came up with the following updates:

   - Driver for the Marvell System Error Interrupt machinery

   - Overhaul of the GIC-V3 ITS driver

   - Small updates and fixes all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits)
  genirq: Fix race on spurious interrupt detection
  softirq: Fix typo in __do_softirq() comments
  genirq: Fix grammar s/an /a /
  irqchip/gic: Unify GIC priority definitions
  irqchip/gic-v3: Remove acknowledge loop
  dt-bindings/interrupt-controller: Add documentation for Marvell SEI controller
  dt-bindings/interrupt-controller: Update Marvell ICU bindings
  irqchip/irq-mvebu-icu: Add support for System Error Interrupts (SEI)
  arm64: marvell: Enable SEI driver
  irqchip/irq-mvebu-sei: Add new driver for Marvell SEI
  irqchip/irq-mvebu-icu: Support ICU subnodes
  irqchip/irq-mvebu-icu: Disociate ICU and NSR
  irqchip/irq-mvebu-icu: Clarify the reset operation of configured interrupts
  irqchip/irq-mvebu-icu: Fix wrong private data retrieval
  dt-bindings/interrupt-controller: Fix Marvell ICU length in the example
  genirq/msi: Allow creation of a tree-based irqdomain for platform-msi
  dt-bindings: irqchip: renesas-irqc: Document r8a7744 support
  dt-bindings: irqchip: renesas-irqc: Document R-Car E3 support
  irqchip/pdc: Setup all edge interrupts as rising edge at GIC
  irqchip/gic-v3-its: Allow use of LPI tables in reserved memory
  ...
parents 4dcb9239 746a923b

Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt

+73 −12
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ The Marvell ICU (Interrupt Consolidation Unit) controller is 
responsible for collecting all wired-interrupt sources in the CP and

communicating them to the GIC in the AP, the unit translates interrupt

requests on input wires to MSG memory mapped transactions to the GIC.

These messages will access a different GIC memory area depending on

their type (NSR, SR, SEI, REI, etc).



Required properties:
@@ -12,20 +14,23 @@ Required properties: 


- reg: Should contain ICU registers location and length.



- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value shall be 3.

Subnodes: Each group of interrupt is declared as a subnode of the ICU,

with their own compatible.



  The 1st cell is the group type of the ICU interrupt. Possible group

  types are:

Required properties for the icu_nsr/icu_sei subnodes:



   ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure

   ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure

   ICU_GRP_SEI (0x4) : System error interrupt

   ICU_GRP_REI (0x5) : RAM error interrupt

- compatible: Should be one of:

              * "marvell,cp110-icu-nsr"

	      * "marvell,cp110-icu-sr"

	      * "marvell,cp110-icu-sei"

	      * "marvell,cp110-icu-rei"



  The 2nd cell is the index of the interrupt in the ICU unit.

- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value shall be 2.



  The 1st cell is the index of the interrupt in the ICU unit.



  The 3rd cell is the type of the interrupt. See arm,gic.txt for

  The 2nd cell is the type of the interrupt. See arm,gic.txt for

  details.



- interrupt-controller: Identifies the node as an interrupt
@@ -35,17 +40,73 @@ Required properties: 
  that allows to trigger interrupts using MSG memory mapped

  transactions.



Note: each 'interrupts' property referring to any 'icu_xxx' node shall

      have a different number within [0:206].



Example:



icu: interrupt-controller@1e0000 {

	compatible = "marvell,cp110-icu";

	reg = <0x1e0000 0x10>;

	reg = <0x1e0000 0x440>;



	CP110_LABEL(icu_nsr): interrupt-controller@10 {

		compatible = "marvell,cp110-icu-nsr";

		reg = <0x10 0x20>;

		#interrupt-cells = <2>;

		interrupt-controller;

		msi-parent = <&gicp>;

	};



	CP110_LABEL(icu_sei): interrupt-controller@50 {

		compatible = "marvell,cp110-icu-sei";

		reg = <0x50 0x10>;

		#interrupt-cells = <2>;

		interrupt-controller;

		msi-parent = <&sei>;

	};

};



node1 {

	interrupt-parent = <&icu_nsr>;

	interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;

};



node2 {

	interrupt-parent = <&icu_sei>;

	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;

};



/* Would not work with the above nodes */

node3 {

	interrupt-parent = <&icu_nsr>;

	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;

};



The legacy bindings were different in this way:



- #interrupt-cells: The value was 3.

	The 1st cell was the group type of the ICU interrupt. Possible

	group types were:

	ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure

	ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure

	ICU_GRP_SEI (0x4) : System error interrupt

	ICU_GRP_REI (0x5) : RAM error interrupt

	The 2nd cell was the index of the interrupt in the ICU unit.

	The 3rd cell was the type of the interrupt. See arm,gic.txt for

	details.



Example:



icu: interrupt-controller@1e0000 {

	compatible = "marvell,cp110-icu";

	reg = <0x1e0000 0x440>;



	#interrupt-cells = <3>;

	interrupt-controller;

	msi-parent = <&gicp>;

};



usb3h0: usb3@500000 {

node1 {

	interrupt-parent = <&icu>;

	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;

};

Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
Marvell SEI (System Error Interrupt) Controller

-----------------------------------------------



Marvell SEI (System Error Interrupt) controller is an interrupt

aggregator. It receives interrupts from several sources and aggregates

them to a single interrupt line (an SPI) on the parent interrupt

controller.



This interrupt controller can handle up to 64 SEIs, a set comes from the

AP and is wired while a second set comes from the CPs by the mean of

MSIs.



Required properties:



- compatible: should be one of:

              * "marvell,ap806-sei"

- reg: SEI registers location and length.

- interrupts: identifies the parent IRQ that will be triggered.

- #interrupt-cells: number of cells to define an SEI wired interrupt

                    coming from the AP, should be 1. The cell is the IRQ

                    number.

- interrupt-controller: identifies the node as an interrupt controller

                        for AP interrupts.

- msi-controller: identifies the node as an MSI controller for the CPs

                  interrupts.



Example:



        sei: interrupt-controller@3f0200 {

                compatible = "marvell,ap806-sei";

                reg = <0x3f0200 0x40>;

                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;

                #interrupt-cells = <1>;

                interrupt-controller;

                msi-controller;

        };

Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt

+4 −1
Original line number Diff line number Diff line
@@ -2,10 +2,12 @@ DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller 


Required properties:



- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.

- compatible: must be "renesas,irqc-<soctype>" or "renesas,intc-ex-<soctype>",

	      and "renesas,irqc" as fallback.

  Examples with soctypes are:

    - "renesas,irqc-r8a73a4" (R-Mobile APE6)

    - "renesas,irqc-r8a7743" (RZ/G1M)

    - "renesas,irqc-r8a7744" (RZ/G1N)

    - "renesas,irqc-r8a7745" (RZ/G1E)

    - "renesas,irqc-r8a77470" (RZ/G1C)

    - "renesas,irqc-r8a7790" (R-Car H2)
@@ -19,6 +21,7 @@ Required properties: 
    - "renesas,intc-ex-r8a77965" (R-Car M3-N)

    - "renesas,intc-ex-r8a77970" (R-Car V3M)

    - "renesas,intc-ex-r8a77980" (R-Car V3H)

    - "renesas,intc-ex-r8a77990" (R-Car E3)

    - "renesas,intc-ex-r8a77995" (R-Car D3)

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

arch/arm64/Kconfig.platforms

+1 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ config ARCH_MVEBU 
	select MVEBU_ICU

	select MVEBU_ODMI

	select MVEBU_PIC

	select MVEBU_SEI

	select OF_GPIO

	select PINCTRL

	select PINCTRL_ARMADA_37XX

drivers/base/platform-msi.c

+8 −6
Original line number Diff line number Diff line
@@ -321,8 +321,9 @@ void *platform_msi_get_host_data(struct irq_domain *domain) 
 * Returns an irqdomain for @nvec interrupts

 */

struct irq_domain *

platform_msi_create_device_domain(struct device *dev,

__platform_msi_create_device_domain(struct device *dev,

				    unsigned int nvec,

				    bool is_tree,

				    irq_write_msi_msg_t write_msi_msg,

				    const struct irq_domain_ops *ops,

				    void *host_data)
@@ -336,7 +337,8 @@ platform_msi_create_device_domain(struct device *dev, 
		return NULL;



	data->host_data = host_data;

	domain = irq_domain_create_hierarchy(dev->msi_domain, 0, nvec,

	domain = irq_domain_create_hierarchy(dev->msi_domain, 0,

					     is_tree ? 0 : nvec,

					     dev->fwnode, ops, data);

	if (!domain)

		goto free_priv;

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